Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
1999-12-22
2002-04-30
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S130000, C438S600000, C438S622000, C438S637000, C438S638000, C438S639000, C438S640000, C257S530000
Reexamination Certificate
active
06380003
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnect structures, and more particularly to interconnect structures such as anti-fuse structures in which an anti-fuse material is formed within a slot via to provide a connection between various conductive levels present in the interconnect structure.
BACKGROUND OF THE INVENTION
The manufacture of integrated circuits (ICs) typically includes the formation of metallization layers which are patterned to provide interconnection between devices. Some IC interconnections are programmable, either with fuses or anti-fuses. Unprogrammed fuses provide a low resistance link between or within metallization layers which can be programmed by being blown. That is, the fuse can be caused to be non-conductive by applying a sufficiently high current across it to blow.
Anti-fuses operate in the opposite fashion, i.e., the unprogrammed structure used to form the anti-fuse has an intrinsically high resistance, and the programmed structure has a relatively low resistance. By applying a programmable current of, for example, 1 mA, the electrical resistance through the anti-fuse material is greatly reduced providing a conductive link between or within metallization levels. Typical prior art anti-fuse materials include: amorphous silicon, amorphous carbon, carbon, germanium, selenium, compound semiconductors such as GaAs, SiC, AIP, InSb and CdTe, and ceramics such as Al
2
O
3
.
One prior art anti-fuse structure is shown in FIG.
1
. Specifically, the structure shown in
FIG. 1
comprises a substrate
12
such as a Si wafer. An oxide layer
14
overlays the substrate, and can be formed by a variety of well known deposition processes such as chemical vapor deposition. A metal layer
16
is then formed on the oxide layer utilizing conventional deposition processes such as evaporation or sputtering. A second oxide layer
18
is formed over the metal layer and a via
20
is formed in the second oxide layer utilizing conventional lithography and reactive-ion etching (RIE). One of the above mentioned anti-fuse materials is then formed in the via to form an anti -fuse structure
22
. A second metal layer
24
is then formed over the structure.
Programming of the anti-fuse structure of
FIG. 1
can be accomplished by providing a current of about 10 mA between the metal layers. Before programming, the anti-fuse structure typically has a resistance of above 1 giga-ohm for a 1 &mgr;m diameter via. A programmed anti-fuse forms a conductive path
26
between the metal layers having a resistance of about 20-100 ohms.
Anti-fuse structures allow for much higher programmable interconnection densities than standard fuse structures. A major problem with prior art anti-fuse structures is that dedicated lithographic masking levels are required to fabricate the same. Not only does the use of such dedicated lithographic masking levels add additional cost to the overall process, but it adds to the complexity of the same.
In view of the above mentioned problems with prior art anti-fuse structures, there is a continued need to develop a new and improved method in which an anti-fuse structure is fabricated without employing dedicated lithographic masking levels.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating an interconnect structure in which an anti-fuse material is formed between various conductive levels of the structure without the need of employing dedicated lithographic masking levels.
Another object of the present invention is to provide a method in which the anti-fuse material is formed in a slot via that is present in an interlevel dielectric layer of an interconnect structure; the slot via consists of an enlarged contact via which provides increase in overlay tolerance with the next layer contact via.
A still further object of the present invention is to provide a method in which an anti-reflective coating is employed as the anti-fuse material.
These and other objects and advantages are achieved in the present invention by employing the following method which includes the steps of:
(a) providing a substrate having a first level of electrically conductive features formed therein;
(b) forming an interlevel dielectric material on said first level of electrically conductive features, said interlevel dielectric material having an upper surface;
(c) forming vias in said interlevel dielectric material to expose portions of said first level of electrically conductive features, wherein at least one of said vias is a slot via;
(d) applying a conformal anti-fuse material on said interlevel dielectric material;
(e) applying a photoresist on said anti-fuse material;
(f) patterning said photoresist, said patterned photoresist containing spaces corresponding to positions for a second level of electrically conductive features;
(g) etching said substrate, whereby portions of said anti-fuse material are removed from said spaces;
(h) stripping said photoresist;
(i) filling spaces in said interlevel dielectric material with a conductive material, whereby said second level of electrically conductive features is formed, said second level of electrically conductive features and said first level of electrically conductive features being connected by said anti-fuse material; and
(j) removing portions of said anti-fuse material at the upper surface of said interlevel dielectric material, whereby portions of said anti-fuse material remain over a portion of said first level of said electrically conductive features in said slot via.
The above processing steps may be repeated any number of times providing a multilevel interconnect structure in which the anti-fuse material is formed in the slot vias of various interlevel dielectric layers.
In an optional embodiment of the present invention, a barrier layer is formed in the interlevel dielectric spaces prior to filling the spaces with a conductive material. This typically occurs between steps (h) and (i) above and is used when the first and second levels of electrically conductive features are wiring levels of an interconnect structure.
The present invention also provides interconnect structures in which the anti-fuse material is formed in a slot via so as to provide a connection between a first level of electrically conductive features and a second level of electrically conductive features. Specifically, the interconnect structure of the present invention comprises:
a substrate having a first level of electrically conductive features formed thereon;
a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and
a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features.
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patent: 5578836 (1996-11-01), Husher et al.
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patent: 6087677 (2000-07-01), Wu
Jahnes Christopher V.
Narayan Chandrasekhar
Radens Carl J.
Capella Steven
Nguyen Ha Tran
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