Damage free buried contact using salicide technology

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257384, 257754, 257755, 257757, H01L 2976, H01L 2994, H01L 2348, H01L 2352

Patent

active

058442847

ABSTRACT:
A semiconductor cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.

REFERENCES:
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patent: 5064776 (1991-11-01), Roberts
patent: 5126285 (1992-06-01), Kosa et al.
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5198378 (1993-03-01), Rodder et al.
patent: 5348896 (1994-09-01), Jang et al.
"Limitation of Spacer Thickness in Titanium Salicide ULSI CMOS Technology", Janmye James Sung and Chih-Yuan Lu, IEEE Electron Device Letters, vol. 10, No. 11, Nov. 1989, pp. 481-483.
Trap et al., "Trends in Plasma Etch Chemistry", Semiconductor Technology Handbook, Photo & Etch, pp. 4-21.

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