Damage-free ashing process and system for post low-k etch

Details Damage-free ashing process and system for post low-k etch Damage-free ashing process and system for post low-k etch

2007-10-09

2007-10-09

Lee, Hsien-Ming (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S711000

Reexamination Certificate

active

11195854

ABSTRACT:
A process is provided for substrate ashing following the etching of features in a low dielectric constant (low-k) layer. The low-k layer can include ultra-low-k material, or a porous low-k material. The process may be configured to remove etch byproducts while preserving feature critical dimension. The ashing process comprises the use of a nitrogen and hydrogen containing chemistry with a passivation chemistry that includes oxygen, such as O2, CO, or CO2, or any combination thereof.

REFERENCES:
patent: 5888337 (1999-03-01), Saito
patent: 2002/0058397 (2002-05-01), Smith et al.
patent: 2004/0180269 (2004-09-01), Balassubramaniam
patent: 2004/0185380 (2004-09-01), Igarashi
patent: 2005/0029229 (2005-02-01), Chae et al.
patent: 2006/0051947 (2006-03-01), Lin et al.
patent: 2006/0138399 (2006-06-01), Itano et al.

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