Daisy chain cascade configuration recognition technique

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711SE12069

Reexamination Certificate

active

08069328

ABSTRACT:
Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

REFERENCES:
patent: 4174536 (1979-11-01), Misunas et al.
patent: 4617566 (1986-10-01), Diamond
patent: 4733376 (1988-03-01), Ogawa
patent: 4796231 (1989-01-01), Pinkham
patent: 4899316 (1990-02-01), Nagami
patent: 5038299 (1991-08-01), Maeda
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5132635 (1992-07-01), Kennedy
patent: 5136292 (1992-08-01), Ishida
patent: 5175819 (1992-12-01), Le Ngoc et al.
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5280539 (1994-01-01), Yeom et al.
patent: 5319598 (1994-06-01), Aralis et al.
patent: 5365484 (1994-11-01), Cleveland et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5440694 (1995-08-01), Nakajima
patent: 5452259 (1995-09-01), McLaury
patent: 5473563 (1995-12-01), Suh et al.
patent: 5473566 (1995-12-01), Rao
patent: 5473577 (1995-12-01), Miyake et al.
patent: 5475854 (1995-12-01), Thomsen et al.
patent: 5596724 (1997-01-01), Mullins et al.
patent: 5602780 (1997-02-01), Diem et al.
patent: 5636342 (1997-06-01), Jeffries
patent: 5671178 (1997-09-01), Park et al.
patent: 5721840 (1998-02-01), Soga
patent: 5740379 (1998-04-01), Hartwig
patent: 5761146 (1998-06-01), Yoo et al.
patent: 5771199 (1998-06-01), Lee
patent: 5802006 (1998-09-01), Ohta
patent: 5806070 (1998-09-01), Norman et al.
patent: 5818785 (1998-10-01), Ohshima
patent: 5828899 (1998-10-01), Richard et al.
patent: 5835935 (1998-11-01), Estakhri et al.
patent: 5859809 (1999-01-01), Kim
patent: 5872994 (1999-02-01), Akiyama et al.
patent: 5937425 (1999-08-01), Ban
patent: 5938750 (1999-08-01), Shaberman
patent: 5941974 (1999-08-01), Babin
patent: 5959930 (1999-09-01), Sakurai
patent: 5995405 (1999-11-01), Trick
patent: 5995417 (1999-11-01), Chen et al.
patent: 6002638 (1999-12-01), John
patent: 6085290 (2000-07-01), Smith et al.
patent: 6091660 (2000-07-01), Sasaki et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6144579 (2000-11-01), Taira
patent: 6148364 (2000-11-01), Srinivasan et al.
patent: 6172911 (2001-01-01), Tanaka et al.
patent: 6178135 (2001-01-01), Kang
patent: 6304921 (2001-10-01), Rooke
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6378018 (2002-04-01), Tsern et al.
patent: 6438064 (2002-08-01), Ooishi
patent: 6442098 (2002-08-01), Kengeri
patent: 6535948 (2003-03-01), Wheeler et al.
patent: 6584303 (2003-06-01), Kingswood et al.
patent: 6594183 (2003-07-01), Lofgren et al.
patent: 6601199 (2003-07-01), Fukuda et al.
patent: 6611466 (2003-08-01), Lee et al.
patent: 6658509 (2003-12-01), Bonella et al.
patent: 6658582 (2003-12-01), Han
patent: 6680904 (2004-01-01), Kaplan et al.
patent: 6715044 (2004-03-01), Lofgren et al.
patent: 6718432 (2004-04-01), Srinivasan
patent: 6732221 (2004-05-01), Ban
patent: 6754807 (2004-06-01), Parthasarathy et al.
patent: 6763426 (2004-07-01), James et al.
patent: 6807103 (2004-10-01), Cavaleri et al.
patent: 6816933 (2004-11-01), Andreas
patent: 6850443 (2005-02-01), Lofgren et al.
patent: 6853557 (2005-02-01), Haba et al.
patent: 6853573 (2005-02-01), Kim et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6967874 (2005-11-01), Hosono
patent: 7058757 (2006-06-01), Branth et al.
patent: 7073022 (2006-07-01), El-Batal et al.
patent: 7170795 (2007-01-01), Lee
patent: 2003/0074505 (2003-04-01), Andreas et al.
patent: 2003/0128702 (2003-07-01), Satoh et al.
patent: 2004/0001380 (2004-01-01), Becca et al.
patent: 2004/0019736 (2004-01-01), Kim et al.
patent: 2004/0024960 (2004-02-01), King et al.
patent: 2004/0039854 (2004-02-01), Estakhri et al.
patent: 2004/0153914 (2004-08-01), El-Batal
patent: 2004/0199721 (2004-10-01), Chen
patent: 2004/0230738 (2004-11-01), Lim et al.
patent: 2004/0268025 (2004-12-01), Matsubara et al.
patent: 2005/0035895 (2005-02-01), Byrne et al.
patent: 2005/0086413 (2005-04-01), Lee et al.
patent: 2005/0095769 (2005-05-01), Takase et al.
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2005/0213421 (2005-09-01), Polizzi et al.
patent: 2006/0050594 (2006-03-01), Park
patent: WO 01/69411 (2001-09-01), None
“Toshiba MOS Digital Integrated Circuit Silicon Gate CMOS,” TH58NVG1S3AFT05, Toshiba Corporation, pp. 1-32, (May 19, 2003).
“Intel® Advanced+ Boot Block Flash Memory (C3),” Intel Corporation, pp. 1-72, (May 2005).
“256 M × 8 Bit/ 128M ×16 Bit / 512M × 8 Bit NAND Flash Memory,” K9K4G08U1M, K9F2G08U0M, K9F2G16U0M, Rev. 1.0, Samsung Electronics Co., Ltd., pp. 1-41, (May 6, 2005).
King, et al., “Communicating with Daisy Chained MCP42XXX Digital Potentiometers”, Microchip AN747, pp. 1-8, 2001.
“High Speed Small Sectored SPI Flash Memory,” Atmel Corp., pp. 1-22 (2006).
64 Megatbit CMOS 3.0 Volt Flash Memory with 50MHz SPI (2006).
“DiskOnChip H1 4Gb (512MByte) and 8 Gb (1 GByte) High Capacity Flash Disk with NAND and x2 Technology,” Data Sheet, Rev. 0.5 (Preliminary), M-Systems Flash Disk Pioneers Ltd., pp. 1-66, (2005).
Tal, A., “Guidelines for Integrating DiskOnChip in a Host System,” AP-DOC-1004, Rev. 1.0, M-Systems Flash Disk Pioneers Ltd., pp. 1-15, (2004).
OneNAND4G(KFW4G16Q2M-DEB6), OneNAND2G(KFH2G16Q2M-DEB6), OneNAND1G(KFW1G16Q2M-DEB6) Flash Memory, OneNAND™ Specification Ver. 1.2, Samsung Electronics, pp. 1-125, (Dec. 23, 2005).
Kennedy, J., et al., “A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems,”ISSCC 2004/Session 1/DRAM/11.8, IEEE International Solid-State Circuits Conference (2004).
Kim, Jae-Kwan, et al., “A 3.6Gb/s/pin Simultaneous Bidirectional (SBD) I/O Interface for High-Speed DRAM”,ISSCC 2004/Session 22/DSL and MULTI-Gb/s I/O 22.7, IEEE International Solid-State Circuits Conference (2004).
“HyperTransport TM I/O Link Specification”, Revision 2.00, Document No. HTC20031217-0036-00, HyperTransportTM Technology Consortium, pp. 1-325 (2001).
“IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink) ”,IEEE Std. 1596.4-1996, The Institute of Electrical Electronics Engineers, Inc., pp. i-91, (Mar. 1996).
“High-Speed Memory Architectures For Multimedia Applications”,Circuits&Devices, IEEE 8755-3996/97/, pp. 8-13, Jan. 1997.
Gjessing, S., et al., “RamLink: A High-Bandwidth Point-to-Point Memory Architecture”, IEEE 0-8186-2655-0/92, pp. 328-331, 1992.
Gjessing, S., et al., “Performance of the RamLink Memory Architecture”,Proceedings of the Twenty-Seventh Annual Hawaii International Conference on System Sciences, IEEE 1060-3425/94, pp. 154-162, 1994.
Gjessing, S., et al., “A RAM link for high speed”,Special Report/Memory, IEEE Spectrum, pp. 52-53, (Oct. 1992).
Diamond, S. L., “SyncLink: High-speed DRAM for the future”,Micro Standards, IEEE Micro, pp. 74-75, (Dec. 1996).
“DDR2 Fully Buffered DIMM 240pin FBDIMMS based on 512Mb C-die”, Rev. 1.3 Sep. 2006, Samsung Electronics, pp. 1-32 (Sep. 2006).
“HyperTransportTM IO Link Specification”, Revision 3.00, Document No. HTC200

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Daisy chain cascade configuration recognition technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Daisy chain cascade configuration recognition technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Daisy chain cascade configuration recognition technique will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4261885

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.