D-type flip-flop with a reduced number of transistors

Details D-type flip-flop with a reduced number of transistors D-type flip-flop with a reduced number of transistors

2006-05-23

2006-05-23

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S203000

Reexamination Certificate

active

07049871

ABSTRACT:
A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback loop with first and second inverter circuits having feedback to one another. The inverting output is coupled to the first inverter circuit output and the non-inverting output is coupled to the second inverter circuit output. The acceptance unit, dependent upon the data and clock signals present, allocates a programming potential to the first or the second inverter circuit input and applies no potential to the respective other input of the circuits. The acceptance unit has a first switching element applying the predetermined programming potential to the input of the first inverter circuit dependent upon the clock and data signals and a second switching element applying the predetermined programming potential to the second inverter circuit input dependent upon the clock and data signals.

REFERENCES:
patent: 6232810 (2001-05-01), Oklobdzija et al.
patent: 6445217 (2002-09-01), Kojima et al.
patent: 6720813 (2004-04-01), Yee et al.
patent: 2003/0006812 (2003-01-01), Collier et al.
patent: SHO 60-224319 (1985-11-01), None
patent: 10093397 (1998-04-01), None

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