D.M.A. device that handles cache misses by managing an address o

Details D.M.A. device that handles cache misses by managing an address o D.M.A. device that handles cache misses by managing an address o

1998-01-15

2000-05-02

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

709212, 710 35, 710 52, 711118, 711133, 345511, G06F 1328

Patent

active

060584378

ABSTRACT:
A direct memory access processing device of communication equipment which has a main memory device and communication equipment including queues storing information related to communications between processs and management tables storing physical addresses in the main memory device allotted to the process, and when information to be managed by a destination process is externally transferred to the communication equipment, retrieves information about the destination process stored in the queues from the management tables, thereby storing the received information in the addresses of the main memory device via a direct memory access, the main memory device comprising an area allotted to a process for the immediate use, and a daemon process wholly responsible for managing the area, and the management table comprising a process record for managing the address of the area allotted in the main memory device for the immediate use.

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U-Net: A User-Level Network Interface for Parallel and Distributed Computing; Thorsten von Eicken, Anindya Basu, Vineet Buch, and Werner Vogels; Department of Computer Science; Cornell University; Ithaca, NY 14853; Aug. 21, 1995; pp. 1-14.

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