D-FF circuit

Details D-FF circuit D-FF circuit

2001-02-23

2002-08-06

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000

Reexamination Certificate

active

06429713

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D-FF circuit. In particular, the present invention relates to a D-FF circuit which is operated in accordance with a clock signal generated by a clock signal generating circuit.
2. Description of the Related Art
According to an earlier development, a D-flip-flop (hereinafter, referred to as “D-FF”) made from CMOS (Complementary MOS) comprises a flip-flop for a master part (hereinafter, referred to as “master FF”), a flip-flop for a slave part (hereinafter, referred to as “slave FF”) and a clock signal generating circuit. The clock signal generating circuit generates a clock signal to output the clock signal to the master FF and the slave FF. The master FF and the slave FF start or stop each operation at each timing in accordance with the outputted clock signal, respectively.
With reference to
FIGS. 4 and 5
, a D-FF circuit
100
according to an earlier development, will be explained.
FIGS. 4A and 4B
are views showing a D-FF circuit made from CMOS according to an earlier development.
FIG. 4A
is a view showing a D-FF circuit
100
.
FIG. 4B
is a view showing a clock signal generating circuit
200
of the D-FF circuit
100
.
FIG. 5
is a timing chart showing an operation of the D-FF circuit
100
according to an earlier development.
In
FIG. 4A
, the D-FF circuit
100
comprises a master FF having inverters
101
and
102
, transfer gates G
11
and G
12
and a NAND gate
106
, and a slave FF having transfer gates G
13
and G
14
, a NAND gate
107
and inverters
103
,
104
and
105
. The master FF and the slave FF start or stop each operation in accordance with the clock signal outputted from the clock signal generating circuit
200
, respectively.
The transfer gates G
11
, G
12
, G
13
and G
14
comprise P-channel transistors Tr
35
to Tr
38
and N-channel transistors Tr
31
to Tr
34
, respectively. The clock signal outputted from the clock signal generating circuit
200
is inputted into each transistor Tr
31
to Tr
38
. Each transfer gate G
11
, G
12
, G
13
and G
14
is in an “ON” state or in an “OFF” state according to the clock signal inputted into each transistor Tr
31
to Tr
38
. These transfer gates hold or transmit an input signal data.
As shown in
FIG. 4B
, the clock signal generating circuit
200
comprises two inverters
201
and
202
. The inverter
201
inverts an input clock signal CLK to output a first clock signal {overscore (CLK
1
)}. The inverter
202
inverts the first clock signal {overscore (CLK
1
)} outputted from the inverter
201
to output a second clock signal CLK
1
.
The transfer gate G
11
connects the output of the inverter
202
of the clock signal generating circuit
200
(the second clock signal CLK
1
) with a gate of the P-channel transistor Tr
35
. Further, the transfer gate G
11
connects the output of the inverter
201
of the clock signal generating circuit
200
(the first clock signal {overscore (CLK
1
)}) with a gate of the N-channel transistor Tr
31
. Therefore, when the second clock signal {overscore (CLK
1
)} is in a “H” level and the first clock signal {overscore (CLK
1
)} is in a “L” level, the transfer gate G
11
is in an “OFF” state and stops the operation of the master FF. The transfer gate G
11
holds an input signal data.
The transfer gate G
13
connects the output of the inverter
201
of the clock signal generating circuit
200
(the first clock signal {overscore (CLK
1
)}) with a gate of the P-channel transistor Tr
37
. Further, the transfer gate G
13
connects the output of the inverter
202
of the clock signal generating circuit
200
(the second clock signal CLK
1
) with a gate of the N-channel transistor Tr
33
. Therefore, when the second clock signal CLK
1
is in a “H” level and the first clock signal CLK
1
is in a “L” level, the transfer gate G
13
is in an “ON” state and starts the operation of the slave FF.
That is, in the D-FF circuit
100
according to an earlier development, the phases of two signals (the first clock signal {overscore (CLK
1
)} and the second clock signal CLK
1
) are inverted. The clock signals are used as a clock signal for stopping the operation of the master FF and a clock signal for starting the operation of the slave FF, respectively.
In the timing chart shown in
FIG. 5
, when a “H” level input signal data is inputted at the time t
40
, the inverter
101
inverts the input signal data to output it. At the time t
41
, the voltage of the input signal data falls from a “H” level to a “L” level at a node N
31
. Because the transfer gate G
11
is in an “ON” state at the same time, the inverted input signal data outputted from the inverter
101
is transmitted. Next, the inverter
102
inverts the signal transmitted from the transfer gate G
11
to output it. Then, at the time t
43
, the voltage of the signal rises from a “L” level to a “H” level at a node N
33
.
On the other hand, when a “H” level input clock signal CLK is inputted into the clock signal generating circuit
200
at the time t
42
, the inverter
201
inverts the input clock signal CLK to output a “L” level first clock signal {overscore (CLK
1
)}. That is, at the time t
44
, the voltage of the first clock signal {overscore (CLK
1
)} falls from a “H” level to a “L” level. The inverter
202
inverts the first clock signal {overscore (CLK
1
)} to output a “H” level second clock signal CLK
1
. That is, at the time t
45
, the voltage of the second clock signal CLK
1
rises from a “L” level to a “H” level.
The transfer gate G
11
is in an “OFF” state by the first clock signal {overscore (CLK
1
)} and the second clock signal CLK
1
at the time t
45
. The operation of the master FF is stopped and the master FF holds the input signal data. At the same time, the transfer gate G
13
is in an “ON” state and starts the operation of the slave FF.
When the operation of the slave FF is started, a “H” level signal passes through a node N
35
at the time t
46
. At the time t
49
, an inverted “L” level output signal {overscore (OUT)} is outputted.
In the above D-FF circuit
100
, an internal set up time which is an effective accessible time for the input signal data is from the time t
40
at which the data is inputted, to the time t
45
at which the operation of the master FF is stopped. An effective internal tpd (Time for Propagation Delay) of the slave FF is the sum of the pass time of the slave FF and the pass time for generating the {overscore (CLK
1
)}, that is, from the time t
45
to the time t
49
. Therefore, the operation speed (time) of the D-FF circuit
100
according to an earlier development is the sum of the set up time and the tpd, that is, from the time t
40
to the time t
49
.
As described above, the D-FF circuit
100
according to an earlier development uses two signal having phases which are inverted each other. One signal stops the operation of the master FF to determine the set up time, and the other starts the operation of the slave FF to determine the tpd. Therefore, the set up time is almost restricted to the pass time of the master FF. The tpd is restricted to the pass time of the slave FF and the pass time for generating the CLK
1
. Because the operation speed of the D-FF circuit is determined by the sum of internal pass time, there is a problem that it is difficult to operate a D-FF circuit at high speed.
SUMMARY OF THE INVENTION
In order to solve the above-described problems, an object of the present invention is to operate a D-FF circuit at high speed in accordance with the clock signal generated by the clock signal generating circuit.
That is, in accordance with one aspect of the present invention, a D-FF circuit (for example, a D-FF circuit shown in
FIG. 1A
) for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit (for example, a clock signal generating circuit
2
shown in
FIG. 1B
or a clock signal generating circuit
2
′ shown in FIG.
3
),
wherein the clock signal generating circuit generates t

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