Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-02-27
2007-02-27
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C234S089000, C234S098000, C234S027000, C341S144000
Reexamination Certificate
active
11128333
ABSTRACT:
A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.
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Azami Munehiro
Koyama Jun
Nagao Shou
Osame Mitsuaki
Tanaka Yukio
Dinh Duc
Hjerpe Richard
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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