Cycle-skipping DRAM for power saving

Details Cycle-skipping DRAM for power saving Cycle-skipping DRAM for power saving

1999-02-22

2001-01-23

Robertson, David L. (Department: 2759)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S143000, C365S222000, C365S227000

Reexamination Certificate

active

06178479

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to dynamic random access memories (DRAMs) used in computer systems. More particularly the invention relates to methods and devices for reducing the power consumed by DRAMs to benefit portable, battery powered equipment.
2. Description of the Prior Art
Dynamic random access memories (DRAM's) are now the main type of memory devise used in computer systems, at least in part, because their one-transistor per memory cell construction permits a maximum of memory storage to be designed onto a chip. Each memory cell uses a capacitor to store a voltage that represents a digital bit value. Because the capacitors are very small, a refresh must be periodically performed to rewrite each bit. Otherwise, the information written in the memory is lost due to drifts and leakage that occur in such circuits. Most such DRAM's use circuits that unavoidably destroy the data in each memory cell when it is read out. Thus, a write-back cycle is needed to return the data to its original condition for other accesses.
It has been common practice in DRAM design to organize the memory cells into equal numbers of rows and columns, forming a square area on the chip die. A 1M-bit DRAM is therefore roughly organized as 1K-by-1K, depending on the height and width of each cell. Access to such memory involves selecting whole rows where only a portion of the whole number of columns are manipulated at any one access. Row decoders are used to select which row in a memory core is to be accessed and column decoders are used to select the columns that match the system memory address. Sense amplifiers and latches are used to read and hold the data values in peripheral circuits, because the way the data are stored in the individual memory cells is incompatible with the external logic levels.
A principle reason that DRAM designers have been interested in reducing the power consumption of devices is to keep the heat dissipation to reasonable levels. With more than a million bits per DRAM chip now common, whatever power is dissipated in each memory cell is multiplied by a million or more for the whole chip. For example, Katsutaka Kimura, et al., describe various power reduction techniques that are conventional in DRAM design in their article,
Power Reduction Techniques in Megabit
DRAM's, IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 3, pp. 381-388 (June 1986). They seem to settle on using CMOS technology with half-Vcc precharge as their preferred solution for DRAMs over 1M-bit.
Another similar discussion is by Kiyoo Itoh, et al. in
Trends in Low-Power RAM Circuit Technologies,
Proceedings of the IEEE, Vol. 83, No. 4, pp. 524-543 (April 1995). This article describes how lowering RAM memory power consumption can be helpful in portable battery powered equipment. The focus is on ways the charging capacitance, operating voltage, and DC static current can all be reduced to save on the overall power consumed by a RAM. A preferred method here for reducing power consumption is to use partial activation of multi-divided data-line and shared I/O circuits.
The popularity of portable computers and devices powered by batteries has been increasing. But batteries with very high energy storage capability continue to elude designers. So the answer to longer operational battery life is to draw less power for a given application. Thus, even in DRAMs where heat dissipation is not a problem, it is nevertheless important to reduce power consumption to extend operating time for portable systems because such a large portion of the overall system power is consumed by the DRAMs.
SUMMARY OF THE INVENTION
A DRAM memory embodiment of the invention saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal memory core. Because each such cycle costs power, skipped cycles save power. Specifically, read cycles are not always automatically followed by write-back cycles that restore the read-data, e.g., due to the destructive-read nature of the DRAM. Such write-back cycles are only allowed when they can be postponed no longer, and the data written are actually used sometime later. Data that are read back only once, and that have thereby served their purpose, are not written-back. Simple refresh cycles involving unused rows or rows that have been destructively read and not yet written-back are skipped and not refreshed. Data rows that are read from the memory core are held in the peripheral circuits in a way that simulates a cache. All the external byte and bit accesses that can be supported by the whole row in cache are serviced without read or write cycles to the memory core.


REFERENCES:
patent: 5283885 (1994-02-01), Hollerbauer
patent: 5656528 (1997-08-01), Wahlstrom
patent: 6028805 (2000-02-01), Higuchi
patent: 6094705 (2000-07-01), Song
Katsutaka Kimura, et al., “Power Reduction Techniques in Megabit DRAM's,” IEEE Journal of Solid-State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 381-388.
Kiyoo Itoh, et al., “Trends in Low-Power RAM Circuit Technologies”, Proceedings of the IEEE, vol. 83, No. 4, Apr. 1995, pp. 524-543.

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