Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-08-01
2001-11-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S010000
Reexamination Certificate
active
06316963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cycle selection circuit, and more particularly to a cycle selection circuit which is capable of changing the cycle of a refresh timer.
2. Description of the Prior Art
Because of the nature of a DRAM being a volatile memory, it has been indispensable that it is adapted to a refresh operation in order to hold the electrical charges on the memory cells.
One type of refresh operation is the self-refresh operation by which refresh operation is conducted by automatically incrementing an internal refresh counter within a refresh cycle time as a result of holding a refresh control terminal provided in the DRAM at a certain prescribed level.
An example of the conventional technique concerning the self-refresh operation has been disclosed as a semiconductor memory storage in Japanese Patent Applications Laid Open, No. Hei 5-1899600.
The semiconductor memory storage disclosed in the document is given a congfiguration in which a fuse that makes the self-refresh cycle adjustable and a switch means that is connected in series with the fuse are provided.
With such a configuration, it is possible to realize the same state as that in which the fuse is disconnected by bringing the switch means to the off-state through application of a prescribed voltage to a control terminal of the switch means, and reinstate the state in which the fuse is not disconnected by returning the switch means to the on-state.
In addition to the above, a synchronous DRAM (SDRAM) which performs a synchronous operation according to a prescribed clock signal has been developed recently by using a DRAM as a basic constituent element.
An example of the conventional technique concerning the SDRAM has been disclosed as a semiconductor memory storage in Japanese Patent Application Laid Open, No. Hei 11-31383.
According to the semiconductor memory storage disclosed in the document, an SDRAM provided with a self-refresh mode and a refresh control circuit, is given a configuration in which the SDRAM is equipped with a refresh cycle control signal input terminal for selectively switching the refresh cycle from the outside in order to switch the refresh cycle in response to the operating frequency.
With such a configuration, the optimum use of an SDRAM at the operating frequency can be realized by selectively switching the refresh cycle in the self-refresh mode of the SDRAM in response to its operating frequency. As a result, reduction in the power consumption and the busy rate of a memory system containing an SDRAM or the like can be achieved.
Besides, the specification of a DRAM is classified according to the charge holding time (tREF) of the memory cells within the chip, and a preliminary wafer test for measuring the tREF to determine the specification is conducted in the assembly step of the semiconductor memory storage.
The preliminary wafer test is carried out by giving a signal having a self-refresh timer cycle to the memory cells within the chip while varying the cycle.
As a result, when cell data can be retained, for example, even when the cycle of the self-refresh timer is increased, namely, when the tREF is made larger than a prescribed limit, it is regarded to have the specification for low current consumption products (low power products), and the X16 I/O products (multi-bit I/O products) among these are served for use in portable equipment.
On the other hand, when the cell data cannot be retained, namely, when the tREF is less than a prescribed value it is regarded to have the specification for normal power products, and the X4 and X8 I/O products among these are served for the use in the power machines.
Moreover, when a defective memory cell is discovered in the preliminary wafer test, the product is saved by means of the redundancy procedure.
By conducting a preliminary wafer test for measuring the REF in this manner, DRAMs are utilized for assembly according to the classification of their specifications.
However, in the conventional semiconductor memory storage disclosed in Japanese Patent Applications Laid Open, No. Hei 5-189960, use of a switch means connected in series with the fuse is presumed in changing the timer cycle.
As a result, it is not possible in this method, after the disconnection of the fuse, to restore the same state as that wherein the fuse is not disconnected, although it is possible prior to the disconnection of the fuse, to realize the same state as that wherein the fuse is disconnected.
Accordingly, even if the memory cell is saved by means of the redundancy technique, after the fuse is disconnected, it is not possible to conduct a preliminary wafer test for the redundancy cell, so that the product is sometimes decided unfit for the use as a low current consumption product and regarded as a defective item.
Furthermore, the feature of the conventional semiconductor memory storage as disclosed in Japanese Patent Applications Laid Open, No. Hei 11-31383 is that the refresh cycle is selectively switched in response to the operating frequency. In this device, it is assumed that the refresh cycle corresponding to the operating frequency is fixed, and a specific power supply voltage level for generating signals with the operating frequency is supplied.
In reality, however, it will not happen in a general purpose product such as an SDRAM that the refresh cycle is variable corresponding to the operating frequency.
Moreover, the above invention assumes that a refresh cycle control signal input terminal for selectively switching the refresh cycle from, the outside is provided. However, in a device demanded to be small-sized, it is not desirable from structural or productivity viewpoint to newly provide an external terminal.
Consequently, the change of the refresh cycle is preferable to be executed with solely the production of low current consumption product in mind rather than according to the operating frequency.
Moreover, the DRAM is saved by means of the redundancy technique when defect in the memory cell is discovered by the preliminary wafer test for cell check.
However, for a device that does not have a check function for the saved redundancy cell, it becomes sometimes clear, depending upon the cell that is saved, that the device cannot retain data. In such a case, the device is handled as a defective product.
Furthermore, even if a chip decided to be inappropriate for a certain specification is confirmed to be suitable for another specification after the fuse for adjusting the refresh timer cycle is disconnected, there has not been available a means for saving the chip. Accordingly, if such a saving means can be found, then the number of defective products can be reduced and flexible handling of a variety of specifications will become feasible.
BRIEF SUMMARY OF THE INVENTION
OBJECTS OF THE INVENTION
It is the object of the present invention to provide, in a circuit which permits to adjust the timer cycle for self-refresh by means of fuse disconnection or the like, a cycle selection circuit which makes it possible to restore the timer cycle after the adjustment to a standard value, and a semiconductor memory storage using the cycle selection circuit.
SUMMARY OF THE INVENTION
The cycle selection circuit according to the present invention is provided with a transfer gate circuit consisting of a transfer gate which let an input signal pass through and another transfer gate which let a standard signal with a standard cycle pass through, a transfer gate selection circuit which selects one of the transfer gates provided in the transfer gate circuit and designate the signal that passes through the selected transfer gate as a selected signal, and a forced control signal generation means which forcibly selects the transfer gate provided in the transfer gate circuit that let the standard signal and designates the standard signal as a selected signal, and outputs either one of the selected signals.
Moreover, the cycle selection circuit according to this invention is provided with a primary transfer gate circuit equippe
Cho James H
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tokar Michael
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