Cycle ready circuit for self-clocking memory device

Details Cycle ready circuit for self-clocking memory device Cycle ready circuit for self-clocking memory device

2005-10-18

2005-10-18

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000, C365S202000, C365S203000, C365S233100, C365S241000

Reexamination Certificate

active

06956789

ABSTRACT:
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

REFERENCES:
patent: 6535045 (2003-03-01), Vangal
patent: 6601121 (2003-07-01), Singh et al.
patent: 6603817 (2003-08-01), Hamamoto et al.
patent: 6631094 (2003-10-01), Ikeda
patent: 2002/0157062 (2002-10-01), Greiner

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