Cycle list based bus cycle resolution checking in a bus bridge v

Details Cycle list based bus cycle resolution checking in a bus bridge v Cycle list based bus cycle resolution checking in a bus bridge v

1997-07-31

1999-08-17

Kizou, Hassan

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 37, 714 43, 710126, 710128, G06F 1100

Patent

active

059387777

ABSTRACT:
In a computer system having a bus bridge connecting a plurality of system buses, a cycle list based bus cycle resolution checking system and method have been disclosed. Each bus in the system is treated as an individual, persistent object. Various bus cycles on system buses are also modeled as objects. Each bus object is configured to detect an initiation of a corresponding bus cycle. An initiator cycle list for holding bus cycles initiated by bus masters, and a target cycle list for storing bus cycles sent to bus targets are also created. Each cycle list itself is treated as an object. These cycle lists combinedly interact with a bus object to verify resolution of an initiator bus cycle. A stimulator object may provide a bus stimulus to each bus object as well as to each cycle list. The stimulator object may read said bus stimulus from a stimulus file of real or simulated buses. In such a case, bus bridge performance and functionality can be tested through externally simulated bus signals. Each bus object may instantiate a corresponding bus cycle state machine object upon detection of an initiated bus cycle and store it in the corresponding cycle list. Finally, the initiator cycle list may pass a pointer from each bus cycle state machine object in the target list to each initiator bus cycle state machine object to verify target data resolution for an initiator cycle.

REFERENCES:
patent: 5790831 (1998-08-01), Lin et al.
patent: 5796968 (1998-08-01), Takamiya
patent: 5815677 (1998-09-01), Goodman

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