Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2000-01-24
2001-01-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Counting
C365S189070, C365S230080
Reexamination Certificate
active
06175535
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to memory devices and in particular to dynamic random access memory (DRAM) devices. Still more particularly, the present invention relates to a cycle control circuit for extending a cycle period of a dynamic memory device subarray and a method of operation thereof.
2. Description of the Related Art
As the computer industry evolves, demands for memory have out-paced the technology of available memory devices. One of these demands is for high speed memory compatibility. Thus, in a computer system, such as a personal computer or other computing system, memory subsystems have become an influential component in the overall performance of a system.
Generally, volatile memories are either dynamic random access memory (DRAM) or static random access memory (SRAM). Typically within a SRAM cell, there are a number of transistors and data is stored by the state of a flip-flop circuit formed by some of the transistors. As long as power is supplied, the flip-flop circuit maintains its data, i.e., refreshing is not required. A DRAM device generally contains a number of subarrays, each of which having a memory cell array of individual memory cells that are typically organized in a matrix fashion of rows and columns. Each memory cell in the DRAM usually has a single transistor and a single capacitor. A data signal written into a DRAM memory cell is stored in its associated capacitor and the logic state of the data signal is determined by the charge level of the capacitor. The capacitor, however, will dissipate its charge over time and requires periodic refreshing to maintain its charge.
The two types of volatile memory devices described above have their respective advantages and disadvantages. With respect to memory speed, the SRAM is generally faster than the DRAM due, partially in part, to the nature of the individual cells. The disadvantage with SRAM, however, is that because there are more transistors that make up each SRAM cell, the SRAM is less dense than a DRAM of the same physical size. To illustrate, SRAMs traditionally have a maximum of one-fourth the number of memory cells of a DRAM that uses the same technology. While the DRAM has the advantage of smaller cells and thus higher cell density, one disadvantage is that the DRAM must periodically refresh its memory cells. When the DRAM refreshes and precharges, access to the cells is prohibited, thus resulting in an increase in access time.
A synchronous DRAM controls the memory operations on the memory cells in each subarray using a cycle control methodology. A cycle time is predefined for memory operations, such as READ and WRITE, that includes the time for completing the memory operation and resetting, i.e., refreshing and precharging, the subarray before the next memory operation on the subarray. The subarray cycle time is dependent on the hardware implementation of the DRAM and the clock speed utilized. The subarray cycle time of DRAMs is also longer than the read/write access time of the DRAMs. For example, utilizing a gigahertz clock speed, the subarray cycle time may be 12 ns (12 clock cycles) while the address access time may be only 3.7ns (about 4 clock cycles). After the memory cells in a DRAM subarray are accessed for either a READ or WRITE operation, all of the array structure within that subarray must be reset. As mentioned previously, during this reset period the subarray cannot be accessed until it is reset completely. Thus, if the same address in a subarray needs to be accessed in a consecutive manner, the second operation must be placed “on hold” until the previous subarray cycle is completed, resulting in a long memory access time.
Accordingly, what is needed in the art is an improved memory access scheme that overcomes the above-discussed limitations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved dynamic random access memory (DRAM) device.
It is another object of the present invention to provide a cycle control circuit for extending a cycle period of a dynamic memory device subarray and a method of operation thereof.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein, a cycle control circuit for use with a memory device subarray is disclosed. The cycle control circuit includes a previous address buffer for storing a last accessed address of the subarray and an address comparator for comparing a current requested address with the last accessed address in the previous address buffer. The cycle control circuit also includes a cycle counter, coupled to the address comparator, that receives a control signal generated by the address comparator and, in response thereto, modifies a reset operation of the subarray. In a related embodiment, the memory device is a synchronous dynamic random access memory (DRAM) device.
The present invention introduces the broad concept of extending a cycle time of a memory device subarray when encountering consecutive memory operations on the same address, thus facilitating more efficient memory access. The novel cycle control circuit disclosed by the present invention significantly reduces the memory access time when the same address in the subarray is accessed by consecutive memory operations. This is accomplished by extending the subarray cycle time, thus delaying the resetting of the subarray to allow multiple READ operations at the same subarray address in one subarray cycle.
In another aspect of the present invention, the method disclosed by the present invention includes applying an address to the subarray and generating control signals for the subarray to produce a data output in response to the address. After producing the data output, the applied address is stored. Next, a new address is received and the new address is compared to the stored address. In response to the stored and new addresses being the same, the reset operation of the subarray is modified to again generate the data output in a shorter period of time.
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5923612 (1999-07-01), Park et al.
patent: 5946265 (1999-08-01), Cowles
patent: 5946269 (1999-08-01), Jang
patent: 6005818 (1999-12-01), Ferrant
Dhong Sang Hoo
Ohkubo Manabu
Onishi Shohji
Takahashi Osamu
Dinh Son T.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Saslys Casimer K.
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