Customizable synthesis of tunable parameters for code...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07900168

ABSTRACT:
An apparatus, method and/or computer readable media automatically generate hardware description language (HDL) code. A design environment is configured to receive a hardware design, the hardware design including a plurality of numerical parameters. A user interface (UI) accepts a designation of a first numerical parameter as a tunable numerical parameter. An HDL code generator detects the designation and instantiates a memory structure to store the first numerical parameter. The HDL code generator also configures an interface of a module of the hardware design to receive a value of the first numerical parameter, and instantiates one or more structures internal to the module to utilize the first numerical parameter. The HDL code generator also determines a second numerical parameter has not been designated as a tunable numerical parameter, in response, instantiates one or more structures to maintain the second numerical parameter as a hard-coded numerical parameter.

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