Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-09-11
2007-09-11
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000, C714S032000
Reexamination Certificate
active
10808000
ABSTRACT:
In one embodiment, the invention may include a logic structure integrated in an integrated circuit (IC), that has a set of bus inputs to generate events, a mask register to select inputs from among the set of bus inputs, a logic register to select logic to apply to the selected inputs and an event output to supply the result of the applied logic. The embodiment may further include a bus interface integrated in the IC and coupled to the logic structure to transmit settable parameters to the mask register and the logic register of the logic structure from an external agent.
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patent: 7100086 (2006-08-01), Kudo et al.
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Baartmans Sean T.
White Bryan R.
Blakely , Sokoloff, Taylor & Zafman LLP
Bonura Tim
Intel Corporation
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