Current steering logic circuits

Details Current steering logic circuits Current steering logic circuits

2001-04-06

2003-05-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S098000

Reexamination Certificate

active

06570409

ABSTRACT:

BACKGROUND OF INVENTION
Background Art
The design of a computer system may be broken down into three parts-system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop, or other logic building block.
A logic building block evaluates its input(s) and outputs a result based on the type of function that the logic building block performs. For example, an AND logic gate, a type of logic building block, outputs logic low whenever one of its inputs is logic low and outputs logic high when all of its inputs are logic high. Alternatively, an OR logic gate outputs logic high whenever one of its inputs is logic high and outputs logic low when all of its inputs are logic low. The number of inputs that a logic building block has is referred to as its “fan-in.” In other words, fan-in refers to the number of devices that are driving another device.
An important aspect of circuit design is how logic building blocks, such as logic gates, are actually implemented in a computer system. A typical approach used to implement logic building blocks is through the use of complementary metal-oxide-semiconductor (“CMOS”) logic families.
CMOS logic families use metal-oxide-semiconductor field-effect (“MOSFET”) transistors. The use of MOSFET transistors is beneficial because almost no current is needed to operate the transistors. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (“PMOS”) transistors and negative-channel metal-oxide semiconductor (“NMOS”) transistors. A transistor is ‘on’ when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched ‘on’ or ‘off’ by the movement of electrons, whereas PMOS transistors can be switched ‘on’ or ‘off’ by the movement of electron vacancies. A MOSFET has a voltage threshold (“V
T
”) value, which is the voltage level at which the MOSFET switches ‘on’ or ‘off.’ Generally, a NMOS transistor switches ‘on’ when there is a high voltage applied to the input of the NMOS transistor and a PMOS transistor switches ‘on’ when there is a low voltage, e.g., ground, applied to the input of the PMOS transistor.
Two types of logic gates are static logic gates and dynamic logic gates. Typically, static logic gates have a PMOS and a NMOS transistor for every input. Therefore, with higher fan-in, static logic gates require increased space since the number of transistors needed increases faster than the number of inputs.
Generally, both types of logic gates operate using voltage mode logic. Voltage mode logic is a type of implementation in which circuit behavior is based on a voltage source.
FIG. 1
shows a prior art embodiment of a static logic gate. Specifically,
FIG. 1
shows an OR gate (
11
).
Inputs IN
1
, IN
2
, . . . , IN
n
serve as inputs to PMOS transistors P
1
, P
2
, . . . , P
n
(
13
,
15
,
17
) (also referred to as “PMOS input transistors”), respectively, where n represents the number of inputs to the OR gate (
11
). Inputs IN
1
, IN
2
, . . . , IN
n
also serves as inputs to NMOS transistors N
1
, N
2
, . . . , N
n
(
19
,
21
,
23
) (referred to as “NMOS input transistors”), respectively, where n represents the number of inputs to the OR gate (
11
).
The PMOS input transistors (
13
,
15
,
17
) are arranged in series with P
1
(
13
) having a terminal connected to high (
25
), i.e., a voltage source, and P
n
(
17
) having a terminal connected to a static node, STAT_NODE. The NMOS input transistors (
19
,
21
,
23
) are arranged in parallel with each NMOS input transistor (
19
,
21
,
23
) having a terminal connected to STAT_NODE and another terminal connected to low (
27
), i.e., ground. Further, wire resistances (
5
) are shown on STAT_NODE since a finite amount of voltage is dissipated on STAT_NODE due to these wire resistances (
5
).
STAT_NODE serves as an input to an inverter (
29
), which, in turn, outputs a logic voltage to an output, OUT, of the OR gate (
11
).
When all the inputs to the OR gate (
11
) are low, the PMOS input transistors (
13
,
15
,
17
) are all switched ‘on,’ and STAT_NODE gets connected to high (
25
) through the PMOS input transistors (
13
,
15
,
17
). In this case, the inverter (
29
) inputs high from STAT_NODE and outputs low to OUT.
When one or more of the inputs to the OR gate (
11
) are high, the corresponding NMOS input transistors switch ‘on’ and the corresponding PMOS input transistors switch ‘off.’ In this case, STAT_NODE gets connected to low (
27
) through the ‘on’ NMOS input transistors. Moreover, since one or more of the PMOS input transistors are ‘off,’ there is no connection between STAT_NODE and high (
25
). Thereafter, the inverter (
29
) inputs low from STAT_NODE and outputs high to OUT.
Dynamic logic gates are often used in place of static logic gates when speed, space, and flexibility are important. Typically, dynamic logic gates use a precharged node that replaces the transistors in series used in static logic gates. The dynamic implementation thus uses lesser space, and speed is increased since wait time for transistor switching is decreased.
Referring to
FIG. 2
, a prior art embodiment of a dynamic logic gate is shown. Specifically,
FIG. 2
shows an OR gate (
10
).
The OR gate (
10
) includes a logic evaluation stage (
12
), which has inputs IN
1
, IN
2
, . . . , IN
n
, which serve as inputs to transistors N
1
, N
2
, . . . , N
n
(
14
,
16
,
18
) (referred to as “input transistors”), where n represents the number of inputs to the OR gate (
10
). Each input transistor (
14
,
16
,
18
) has a terminal connected to dynamic node DYN_NODE, and another terminal connected to a terminal of an NMOS transistor (
20
) that resides outside the logic evaluation stage (
12
) (referred to as “outside NMOS transistor (
20
)”).
The outside NMOS transistor (
20
), in addition to having a terminal connected to select terminals of the input transistors (
14
,
16
,
18
) inside the logic evaluation stage (
12
), has another terminal connected to low (
22
). Moreover, a clock signal, CLK, serves as an input to the outside NMOS transistor (
20
).
DYN_NODE is connected to a terminal of a first PMOS transistor (
24
), and DYN_NODE is also connected to a terminal of a second PMOS transistor (
30
). Additionally, DYN_NODE serves as an input to an inverter (
28
), which, in turn, outputs to both an input of the second PMOS transistor (
30
) and to the output, OUT, of the OR gate (
10
). Further, wire resistances (
19
) are shown on DYN_NODE since a finite amount of voltage is dissipated on DYN_NODE due to these wire resistances (
19
).
The first PMOS transistor (
24
), in addition to having a terminal connected to DYN_NODE, has a terminal connected to high (
26
). The second PMOS transistor (
30
), in addition to having a terminal connected to DYN_NODE, also has a terminal connected to high (
26
). Moreover, CLK serves as an input to the first PMOS transistor (
24
).
When CLK goes low, the first PMOS transistor (
24
) switches ‘on,’ and DYN_NODE gets connected to high (
26
) through the first PMOS transistor (
24
). The inverter (
28
), in turn, inputs high and outputs low to both the input of the second PMOS transistor (
30
) and OUT. Since the input to the second PMOS transistor (

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