Current steering differential write circuit for memory cells

Details Current steering differential write circuit for memory cells Current steering differential write circuit for memory cells

1985-11-21

1987-12-08

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

For complementary information

G11C 700

Patent

active

047121939

ABSTRACT:
A current steering differential write circuit is provided that creates a narrow write pulse width without affecting the read threshold of a memory array. The memory array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of current drain lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. A word line driver circuit is coupled between the first voltage terminal and one of the word lines of each of the rows for selectively applying voltage to the one of the word lines. A current drain circuit is coupled between one of the current drain lines of each of the rows and the second voltage terminal for sinking current from the one of the current drain lines. A sense amplifier is coupled to the bit lines of each of the columns for sensing current in the bit lines. A decoder circuit is coupled to the bit lines for enabling current through the bit lines. A current source is coupled between the second voltage terminal and each of the decode circuits for sinking a read current through the bit lines of each column. The current steering differential write circuit is coupled between the first voltage terminal and the current source and is responsive to the sense amplifier for removing the read current from one of the bit lines during a write mode.

REFERENCES:
patent: 4398268 (1983-08-01), Toyoda

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