Current steering circuits and methods with reduced capacitive ef

Details Current steering circuits and methods with reduced capacitive ef Current steering circuits and methods with reduced capacitive ef

1991-06-28

1992-09-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307542, 307585, 307263, 307270, 364490, 364491, H03K 301

Patent

active

051480654

ABSTRACT:
Capacitance compensation techniques are used to reduce capacitive effects that impact on the performance of current steering circuits (FIG. 1). In an isolation technique (FIGS. 2a-2e), a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In a design variable technique FIGS. 3a-3d), a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique (FIG. 4), a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations (FIGS. 5a-5b), such as fabrication layouts in which the source contact is made within a U-shaped gate (FIG. 5a), and in which moat perimeter is contoured (FIG. 5b) for minimal gate area consistent with standard gate/contact spacing requirements.

REFERENCES:
patent: 4680480 (1987-07-01), Hopta
patent: 4847519 (1989-07-01), Wahl et al.
patent: 4945259 (1990-07-01), Anderson

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