Current source and drain arrangement for magnetoresistive...

Details Current source and drain arrangement for magnetoresistive... Current source and drain arrangement for magnetoresistive...

2001-06-20

2003-07-15

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S189080, C365S198000, C365S214000

Reexamination Certificate

active

06594176

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to magnetoresistive random access memory (MRAM) devices.
BACKGROUND
Semiconductors are used for integrated circuits for electronic applications, including radios, televisions, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use an electron charge to store information.
A more recent development in memory devices involves spin electronics, which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a “1” or “0”. One such spin electronic device is a magnetic random-access memory (MRAM), which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1”, is stored in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment's alignment. The stored state is read from the element by detecting the component's resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix or array structure having rows and columns.
An advantage of MRAMs compared to traditional semiconductor memory devices such as DRAMs is that MRAMs can be made smaller and provide a non-volatile memory. For example, a personal computer (PC) utilizing MRAMs would not have a long “boot-up” time as with conventional PCs that utilize DRAMs. MRAMs permit the ability to have a memory with more memory bits on the chip than DRAMs or flash memories. Also, an MRAM does not need to be refreshed and has the capability of “remembering” the stored data.
Because MRAMs operate differently than traditional memory devices, they introduce design and manufacturing challenges.
SUMMARY OF THE INVENTION
The present invention provides an MRAM device having write pats having substantially the same amount of resistance for each memory cell in the array. Current/voltage control (CVC) circuits arc arranged such that the write paths to each memory cell within an MRAM array have substantially the same length, and therefore have substantially the same amount of resistance.
Disclosed is a preferred embodiment of a memory device, comprising a plurality of memory cells arranged in an array, a plurality of first conductive lines disposed beneath the memory cells, the first conductive lines being positioned in a first direction, a plurality of second conductive lines disposed above the memory cells, the second conductive lines being positioned in a second direction, the memory cells being located at cross-points of the first and second conductive lines, and a plurality of CVC circuits including a current source and a current drain, the CVC circuits being coupled at each end of the first and second conductive lines, wherein the memory cells are addressable by applying a current from one of the CVC circuits to a CVC circuit at the opposite end of the first and second conductive lines, wherein the CVC circuits are arranged so that the length of the first and second conductive lines between each current source and drain is substantially the same for each memory cell addressed.
Also disclosed is a preferred embodiment of a memory device having an array of memory cells coupled to a plurality of first and second conductive lines, the memory device comprising at least one CVC circuit coupled at each end of the first and second conductive lines, each CVC circuit including a current source and a current drain, wherein the CVC circuits are adapted to write information to the memory cells by applying a current from one CVC circuit to a CVC circuit at the opposite end of the first and second conductive lines, wherein the CVC circuits are arranged so that the length of the first and second conductive lines between opposing CVC circuits is substantially the same for each memory cell written to.
Further disclosed is a preferred embodiment of a method of manufacturing a memory device, comprising providing a plurality of memory cells arranged in an array, disposing a plurality of first conductive lines beneath the memory cells, the first conductive lines being positioned in a first direction, disposing a plurality of second conductive lines above the memory cells, the second conductive lines being positioned in a second direction, the memory cells being located at cross-points of the first and second conductive lines, and coupling a plurality of CVC circuits including a current source and a current drain at each end of the first and second conductive lines, wherein the memory cells are addressable by applying a current from one of the CVC circuits to a CVC circuit at the opposite end of the first and second conductive lines, wherein the CVC circuits are arranged so that the resistance of the first and second conductive lines between each current source and drain is substantially the same for each memory cell addressed.
Also disclosed is a preferred embodiment of a method of programming memory cells, comprising passing a first current through a first memory cell in a semiconductor memory device comprising an array of memory cells with a first conductive line, and passing a second current through a second memory cell with a second conductive line, wherein the first and second conductive lines have the substantially the same resistance.
Advantages of preferred embodiments of the invention include providing an arrangement of CVC circuits in MRAMs such that the conductive write path along wordlines and/or bitlines for each memory cell in an MRAM array have substantially the same length: therefore, the write path resistance and write currents for the memory cells in the array are substantially the same, independent of the position of the selected wordline or bitline. This is beneficial because neighboring memory cells are not disturbed when writing to a particular memory cell, which can occur when too high of a write current is used to write to a memory cell. The write margin or selectivity is increased due to the substantially equal write path lengths and resistances, in accordance with embodiments of the invention. Preferred embodiments of the present invention provide an MRAM array where the write current is nearly constant over all word and bitlines, and the resistance along the current path is very uniform. The CVC circuits are arranged so that the resistance or distance to the master wordlines is the same for all memory cells in the array. CVC circuits requiring a smaller amount of current can be utilized in accordance with an embodiment of the present invention.


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