Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-03-07
2001-02-20
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S066000, C365S208000, C365S209000
Reexamination Certificate
active
06191989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to current sensing circuits, and more particularly relates to a two-stage current sensing amplifier capable of detecting small differences in current between two resistances connected to the amplifier.
2. Description of the Prior Art
As described in the article entitled “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell” (ISSCC 2000, Scheuerlein et al.), recent advances in magnetic materials have made magnetic memories, which employ a Magnetic Tunnel Junction (MTJ) memory element in each memory cell, viable contenders for the non-volatile memory market. Desirable characteristics of MTJ based memories include high integration density, high speed, low read power, and SER immunity. Features like these could also advantage MTJ based memories in traditional memory markets dominated by SRAM and DRAM technology. However, in order for an MTJ based memory to compete with these other entrenched technologies, its read access time must be reduced. The present state-of-the-art read access time is “10 ns,” as noted in the paper by Scheuerlein et al. noted above. It is primarily dominated by the time required for sense amplifier circuits to detect the binary state of the data stored in the individual memory cells, once the cells have been selected for read access within the memory array grid.
There remains a need, therefore, in the field of current sensing circuitry, for a current sensing amplifier that not only significantly reduces sensing time, but also reduces the power consumed in the sensing operation. Furthermore, there is a need in the prior art for a current sensing amplifier that can be fabricated on a semiconductor chip using reduced physical area and having a reduced sensitivity to device mismatches, among other environmental factors.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a sensing amplifier that detects small variations in current between two resistances.
It is another object of the present invention to provide a sensing amplifier that performs a high speed current comparison between the two resistances.
It is yet another object of the present invention to provide a current sensing amplifier having a symmetrical configuration to reduce the effects of integrated circuit processing and related variations.
It is a further object of the present invention to provide a current sensing amplifier that is small in physical area and consumes a substantially small amount of power.
The present invention revolutionizes the field of current sensing by providing a current sensing amplifier that not only significantly reduces the overall sense time, but also reduces the power consumed in the sensing operation, the physical area of the sensing amplifier, and the overall sensitivity of the circuit to device mismatches and other environmental factors. These and other improvements are made possible, at least in part, by the integration of self-biased active load field effect transistor (FET) devices and equalization FET devices. The improved current sensing amplifier of the present invention can be employed in a wider range of sensing and measurement applications than just in MTJ based memories. In general, the invention may be applied to the detection of positive and negative signal differences arising between any two resistive loads.
In accordance with one embodiment of the present invention, a current sensing amplifier is provided which comprises a first amplifier, for detecting small differences in current between a pair of resistance loads connected thereto, and a second amplifier for providing enhanced gain and CMOS output voltage levels. The first amplifier includes a voltage clamp operatively connected to a pair of variable resistance loads. The voltage clamp substantially fixes a predetermined voltage across the variable resistance loads and translates a current difference between the loads, superimposed on a common mode current carrier, into a measurable output voltage. The first amplifier further includes a current source operatively connected to the voltage clamp. The current source supplies a constant current to the pair of variable resistance loads, such that the currents in each load are substantially equal to each other. The second amplifier is preferably a high speed gain stage configured as a conventional differential amplifier capable of providing standard CMOS voltage output levels.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings, wherein like elements are designated by identical reference numerals throughout the several views.
REFERENCES:
patent: 5793697 (1998-08-01), Scheuerlein
patent: 6091625 (2000-07-01), Braun et al.
A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell, R. Scheuerlein et al., ISSCC 2000/Sessuib 7 /TD: Emerging Memory & Device Technologies/ Paper TA.2, 2000 IEEE International Solid-State Circuits Conference, pp. 128-129.
Luk Wing Kin
Reohr William Robert
Scheuerlein Roy Edwin
Ellenbogen Wayne L.
Fears Terrell W.
International Business Machines - Corporation
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