Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-08-09
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S121000, C326S112000, C326S105000
Reexamination Certificate
active
06278298
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a current-sense type logic circuit for determining logic based on electric current, and to a semiconductor integrated circuit using such a logic circuit. More particularly, the invention relates to a current-sense type logic circuit with an improved operation speed, and to a semiconductor integrated circuit using this logic circuit, which can increase the operation speed of the entire system of the circuit.
2. Description of the Related Art
In recent years, logic circuits, including CMOS logic circuits, dynamic logic circuits, and pseudo-nMOS logic circuits, tend to have a large number of inputs (and therefore, a large number of logic gates) due to complication of logic.
FIG. 7
illustrates an example of the multi-input logic circuit. This circuit is a pseudo-nMOS logic circuit disclosed in Sun Microsystems, “High-performance Microprocessors” ISSCC97, FA10.2, February 1997.
The pseudo-nMOS logic circuit shown in
FIG. 7
has a logical value determination circuit
100
, a driver
101
for driving the logical value determination circuit
100
, and an inverter
102
.
The driver
101
comprises a CMOS inverter consisting of a p-channel MOSFET PM
1
and an n-channel MOSFET NM
1
. In operation, if a low-level voltage is applied to the gates of the p-channel MOSFET PM
1
and the n-channel MOSFET NM
1
, the MOSFET PM
1
is turned on, while the MOSFET NM
1
remains in the OFF-state. The logic node X of the logical value determination circuit
100
is charged via the MOSFET PM
1
.
The logical value determination circuit
100
includes a plurality of n-channel MOSFETs N(0), N(1), . . . , N(n−1), N(n), which define multiple paths electrically connected in parallel between the logic node X and the ground GND. In this example, the first two paths have two MOSFETs connected in series, and the rest of the paths have a single MOSFET. To be more precise, MOSFETs N(0) and N(1) are connected in series to form a double-transistor path, and MOSFETs N(2) and N(3) are connected in series to form another double-transistor path. The gate of each MOSFET is connected to one of the logic signals IN[1], IN[2], . . . , IN[n−1], IN[n]. The logical inputs are either high (H) or low (L).
Let's consider a case in which high level logic signals IN[1] and IN[3] are applied to the gates of the MOSFET N(1) and N(3), and low level logic signals IN[0], IN[2], IN[4], IN[5], . .. IN[n] are applied to the rest of the MOSFETs. In this case, only two transistors N(1) and N(3) are turned on, while the rest of the transistors remain in the OFF state, and therefore, there are no electric paths existed which ground the logic node X. The logic node X maintains a high voltage charged by the driver
101
and the inverter
102
outputs an inverted value, i.e., a low-level signal.
In general, if a logic holds, the logic is called “TRUE”, which is expressed as a high voltage H (or “1” in binary systems). If a logic does not hold, the logic is called “FALSE”, which is expressed as a low voltage L (or “0” in binary systems). Accordingly, in the above-described case, the logical value output from the pseudo n-MOS logic circuit becomes FALSE.
On the contrary, if there are one or more electric paths formed between the logic node X and the ground GND, the voltage level of the logic node X transits from high to low because of the newly formed current path. Consequently, the inverter
102
outputs a high-level signal, which means that the logical value of this logic circuit is TRUE. This situation occurs if, for example, at least three of IN[0] through IN[3] are high, or alternatively, if at least one of In[4] through In[n] are high, with In[0] through IN[3] low.
Generally, many multi-input pseudo-nMOS logic circuits are incorporated in a semiconductor integrated circuit to form a circuit system. In each multi-input logic circuit, a considerable amount of parasitic capacitance is added to the logic node X because as the number of input gates increases, the total amount of capacitance added to the logic node X becomes large. The parasitic capacitance causes the operation speed to slow down. In the example shown in
FIG. 7
, the parasitic capacitance includes at least the wiring capacitance, and the source, gate, and drain capacitances of the MOSFETs N(0), N(1), . . . , N(n). When driving the logical value determination circuit
100
, the driver
101
must charge the parasitic capacitance also, and the charging time greatly affects the delay time.
If the total amount of parasitic capacitance added to the logic node X is Cp, and the electric current required for the driver
101
to charge the logic node X is Ip, and if the threshold voltage of the inverter
102
is V
dd
/2, then a delay time &Dgr;t from the point of charging the logic node X to the point of actual output of the logical value of the logic circuit is expressed by Equation (1).
&Dgr;t=(Cp×V
dd
)/(2Ip) (1)
It is apparent from Equation (1) that the delay time &Dgr;t increases in proportion to the total amount of parasitic capacitance Cp. As the number of inputs increases due to the complication of logic, the parasitic capacitance inevitably increases in the conventional logic circuit. Accordingly, it was difficult for the conventional technique to implement a high-speed multi-input logic.
If several conventional multi-input logic circuits are incorporated in a semiconductor integrated circuit, the operation speed of the entire integrated circuit system becomes very slow because the operation speed of the integrated circuit system greatly depends on the operation speed of each multi-input logic circuit.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to overcome these problems of the related art, and to provide a multi-input logic circuit that can implement a high-speed operation with a greatly reduced delay time.
It is another object of the invention to provide a logic circuit that has a sufficiently wide range of determination margin for the logical value in order to prevent an error determination, and to improve the reliability of the operation.
It is still another object of the invention to provide a logic circuit that can easily set and produce a reference current used in determination of the logical value.
It is yet another object of the invention to provide a logic circuit having an enhanced driving ability.
It is yet another object of the invention to provide a logic circuit that has a highly improved operation speed with reduced power consumption.
It is yet another object of the invention to provide a high-speed semiconductor integrated circuit using a multi-input logic circuit.
It is still another object of the invention to provide a semiconductor integrated circuit that has an improved reliability in its entire operation.
To achieve the object, in one aspect of the invention, a current-sense type logic circuit comprises a logical value determination, a reference current generator, and a current sense amplifier. The logic value determination circuit defines a logic value as logic current in response to multiple logic signals inputted externally. The reference current generator produces a reference current, which is used to determine logic. The current sense amplifier detects and amplifies a difference between the reference current and the logic current flowing through the logical value determination circuit corresponding to the logical value.
With this arrangement, only the current difference between the reference current and any electric current (i.e., a logic current) flowing in the logical value determination circuit is used to output a result of a logical operation. Unlike the conventional logic circuit, it is not necessary to drive the parasitic capacitance added to a logic node, and to wait until the parasitic capacitance is charged up to the threshold vale.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Paik Steven S.
Tokar Michael
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