Current sense amplifier circuit using dummy bit line

Details Current sense amplifier circuit using dummy bit line Current sense amplifier circuit using dummy bit line

2000-08-04

2001-11-27

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S052000

Reexamination Certificate

active

06323693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a current sense amplifier circuit using a dummy bit line.
2. Description of the Related Art
Basic operations of semiconductor memory devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and flash memories are reading and writing of data. The operations that write data vary according to the type of memory, however, the operations that read data are generally similar because of similarities in memory architectures. In a conventional two-dimensional memory architecture, a word line connects to the gates of memory cell transistors in a row of memory cells, and a bit line connects to the sources or drains of the memory cell transistors in a column of memory cells. The operation of reading data in a typical semiconductor memory device is controlled by a signal, referred to as a read enable signal. A memory cell is selected by enabling a word line and a bit line connected to the memory cell. Therefore, reading data from the memory cell is possible only after the word line and the bit line are enabled.
In a flash memory, data is typically read by sensing the amount of current on a bit line. Therefore, a flash memory uses a current sense amplifier, which can sense and amplify the amount of current, to read data in the flash memory. The time taken for sensing the data stored in the memory cell depends on the time required for the sensed current to reach a stable state. For example, in the case where the word line voltage turns on the cell transistor (i.e., the memory cell transistor is erased and has a low threshold voltage), sensing a stable current greater than a predetermined reference current indicates a first data value. Sensing a stable current less than the reference current (e.g., when the memory cell transistor is programmed to a high threshold voltage) indicates a second data value. A cell in which the memory cell transistor turns on when the corresponding word line is enabled is referred to herein as a turned-on cell. A cell in which the memory cell transistor remains off when the corresponding word line is enabled is referred to herein as a turned-off cell. When the word line is enabled late, the speed at which data is sensed is reduced because a longer wait is required before the sensed current stabilizes.
FIG. 1
illustrates the operation of sensing data in the case of a turned-off cell in a conventional current sense amplifier circuit in a flash memory. Referring to
FIG. 1
, the x axis denotes data sensing time, and the y axis denotes the amount of current which flows through the bit line or the reference cell. Also, reference numerals T
1
,
12
, and
14
respectively denote the time at which data is sensed, the reference current, and the bit line current. The reference current
12
maintains a uniform value, however, the bit current
14
has a large magnitude at an initial stage when the bit line is being charged. The conventional current sense amplifier circuit can sense data only when the component of the bit line current
14
that charges the bit line falls to a certain level with respect to the reference current
12
. If reading is attempted to early, the conventional current sense amplifier circuit can read a turned-off cell as being in the state of a turned-on cell due to an excessive amount of current generated while the bit line is charging.
SUMMARY OF THE INVENTION
The present invention provides a current sense amplifier circuit capable of sensing data within a short time regardless of the amount of bit line charge current in the case of a turned-off cell. In one embodiment of the invention, a current sense amplifier circuit includes a cell current generator, a reference current generator, and a sense amplifier. The cell current generator comprises a memory cell connected to a word line and a bit line and generates memory cell current applied to the memory cell and bit line charge current for charging the bit line. The reference current generator comprises a dummy bit line and a predetermined reference cell and generates a reference cell current applied to the reference cell and a dummy bit line charge current for charging the dummy bit line. The sense amplifier comprises a first input terminal connected to the cell current generator, for receiving the memory cell current and the bit line charge current and a second input terminal connected to the reference current generator, for receiving the reference cell current and the dummy bit line charge current. The sense amplifier senses and amplifies the difference between current applied through the first input terminal and current applied through the second input terminal.


REFERENCES:
patent: 5191552 (1993-03-01), Nakai et al.
patent: 5559737 (1996-09-01), Tanaka et al.
patent: 5717640 (1998-02-01), Hashimoto
patent: 5886546 (1999-03-01), Hwang
patent: 6163484 (2000-12-01), Uekubo

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