Current sense amplifier

Details Current sense amplifier Current sense amplifier

2003-03-04

2004-12-28

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S051000

Reexamination Certificate

active

06836155

ABSTRACT:

PRIORITY STATEMENT
This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application 2002-14814, filed on Mar. 19, 2002, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a current sense amplifier capable of being operated in a stable manner at a low power voltage.
2. Description of the Related Art
In general, a current sense amplifier has an advantage over a voltage sense amplifier, since it operates at a higher speed, as compared to the voltage sense amplifier. Thus, the current sense amplifier can sense and amplify even small amounts of current. Accordingly, current sense amplifiers are often used in high-speed semiconductor devices. However, a common problem with the current sense amplifier is that it typically malfunctions at low power voltages (e.g., lower than power supply voltages used for normal operations).
FIG. 1
illustrates a circuit diagram of a conventional current sense amplifier As shown in
FIG. 1
, the conventional current sense amplifier contains a first PMOS input transistor P
1
and a second PMOS input transistor P
2
. Each PMOS input transistor P
1
and P
2
has a source connected to an input signal line of a pair of input signal lines INL, INLB, a gate and a drain cross-coupled to the drain and the gate of the other PMOS transistor P
1
or P
2
, respectively. References INL and INLB designate an input signal line and a complementary input signal line, respectively. The drains of the first and second PMOS transistors P
1
and P
2
are connected to first and second nodes n
1
and n
2
, where an output signal CSA and a complementary output signal CSAB are respectively output.
The conventional sense amplifier further includes a first NMOS transistor N
1
and a second NMOS transistor N
2
, each with a drain connected to the first node n
1
and the second node n
2
, respectively, each with a gate coupled to its own drain, and each NMOS transistor having a source coupled to a common node n
3
. The current sense amplifier further includes a third NMOS transistor N
3
with a drain connected to the common node n
3
, a gate receiving an enabling signal EN and a source connected to a ground voltage.
Operation of the conventional sense amplifier shown in
FIG. 1
is described below. In operation, the conventional sense amplifier assumes that current i
1
of the input signal line INL is slightly greater than current i
2
of the complementary input signal line INLB. When an enabling signal (EN) with logic “high” level is applied to the gate of the third NMOS transistor N
3
, the third NMOS transistor N
3
is turned on and the common node n
3
becomes the ground voltage.
When voltage differences between the common node n
3
and the first node n
1
, and between the common node n
3
and the second node n
2
, are greater than threshold voltages of the first and second NMOS transistors N
1
, N
2
, respectively, and when voltage differences between the input signal line INL and the first node n
1
and between the complementary input signal line INLB and the second node n
2
are greater than threshold voltages of the first and second PMOS transistors P
1
, P
2
, respectively, the PMOS transistors P
1
and P
2
are turned on. Accordingly, the currents i
1
, i
2
flow to NMOS transistors N
1
and N
2
via PMOS transistors P
1
and P
2
, respectively.
At this time, voltage at the first node n
1
is greater than voltage at the second node n
2
, because the current i
1
of the input signal line INL is greater than the current i
2
of the complementary input signal line INLB, and since resistance of the NMOS transistors N
1
and N
2
are the same. Therefore, resistance of the second PMOS transistor P
2
becomes greater than resistance of the first PMOS transistor P
1
. As a result, a voltage difference between the first node n
1
and second node n
2
occurs. That is, voltage of the second node n
2
is greater than voltage of the first node n
1
. However, this voltage difference value is small.
Operation of the circuit in
FIG. 1
in which the current i
1
is less than the current i
2
is now described. When the enable signal (EN) having a “high” logic level is applied to the gate of the third NMOS transistor N
3
, the common node n
3
becomes the ground voltage. Then, if voltage differences between the common node n
3
and each of the first and the second nodes n
1
, n
2
, respectively, are greater than threshold voltages of the first and second NMOS transistors N
1
, N
2
, respectively, and if voltage differences between the input signal line INL and the first node n
1
and between the complementary input signal line INLB and the second node n
2
are greater than threshold voltages of the first and second PMOS transistors P
1
, P
2
, respectively, the PMOS transistors P
1
and P
2
are turned on. Accordingly, currents i
1
, i
2
flow to the NMOS transistors N
1
and N
2
via PMOS transistors P
1
and P
2
, respectively.
At this time, voltage at the first node n
1
is less than voltage at the second node n
2
because the current i
1
on the input signal line INL is less than the current i
2
on the complementary input signal line INLB, and resistance of the NMOS transistors N
1
and N
2
are the same. Therefore, resistance of the first PMOS transistor P
1
becomes greater than resistance of the second PMOS transistor P
2
. As a result, a voltage difference between the first node n
1
and the second node n
2
occurs. That is, voltage of the second node n
2
is greater than the first node n
1
. However, this voltage difference value is also small.
The conventional current sense amplifier circuit of
FIG. 1
senses small amounts of current on the pair of the input signal lines INL, INLB, and generates a pair of output signals CSA, CSAB, each having a different voltage level. The current sense amplifier in
FIG. 1
may be operated normally if the voltage of each of the input signal lines INL and INLB is greater than a total threshold voltage of the first PMOS transistor P
1
and the second NMOS transistor N
2
, and greater than a total threshold voltage of the second PMOS transistor P
2
and the first NMOS transistor N
1
. For example, if the threshold voltage of the PMOS transistors P
1
, P
2
and the NMOS transistors N
1
, N
2
is 0.8 V, respectively, the current sense amplifier in
FIG. 1
may be normally operated when the voltage level of the input signal lines INL, INLB is greater than 1.6 V. In other words, if the voltage level of the input signal lines INL, INLB is less than 1.6 V, the current sense amplifier in
FIG. 1
may not operate normally.
Therefore, the current sense amplifier of
FIG. 1
may not be utilized for a semiconductor memory device that operates at a low power supply voltage (e.g., less than 1.6 V, for example). As the power supply voltage decreases to below 1.6 V, voltages of the input signal lines INL, INLB also decrease. However, threshold voltages of the PMOS and NMOS transistors should also decrease, for the current sense amplifier of
FIG. 1
to be operated normally In practice, however, it is difficult to reduce the threshold voltage of the transistors.
SUMMARY OF THE INVENTION
Exemplary embodiments of the present invention provide a current sense amplifier capable of being operated normally in low voltage semiconductor devices (devices operated at a voltage less than 1.6 V). An exemplary embodiment is directed to a current sense amplifier that includes a pair of cross-coupled transistors, each transistor being connected between a respective input signal line and a respective output signal generating node, for amplifying voltage difference between the output signal generating nodes. Additionally, the current sense amplifier may include a constant current circuit connected between the output signal generating nodes and a common node for allowing current to flow between the common node and the output signal generating nodes in response to a bias voltage; and a voltage generating circuit for causing a voltage diff

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