Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
1999-12-16
2001-03-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C307S402000
Reexamination Certificate
active
06205070
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit as described in the precharacterizing part of claim
1
.
2. Description of Related Art
U.S. Pat. No. 5,253,137 discloses a memory with a current sense amplifier. The current sense amplifier adjusts the currents drawn from a pair of complementary bitlines so that the potential difference between the bitlines remains constantly zero. The current difference is used to generate a memory output signal. By keeping the potential difference between the bitlines constant, delays needed for charging and equalizing the bitlines are avoided.
The memory according to U.S. Pat. No. 5,253,137 has two power supply connections. Inputs of the sense amplifiers are connected to the first power supply connection via respective ones of the bit lines. The sense amplifier contains two current branches. Each input of the sense amplifier is connected to the second power supply connection via its own current branch. Each current branch contains the source/drain channel of a PMOS input transistor and a PMOS load transistor successively between the bitline and the second power supply connection. The gate of the input transistor in the each branch is cross-coupled to the drain of the input transistor in the other current branch. The gates of the load transistor are coupled to the second power supply connections.
In operation, the sense amplifier equalizes the voltage drop from the inputs of the sense amplifier to the second power supply connection, which forms a common node for the two branches. The gate/source voltage of the input transistor and the load transistor in the same current branch are substantially equal because they draw the same current. The cross-coupling ensures that the voltage drop across each current branch is the sum of the gate source voltage drops of one transistor from each branch.
This circuit has the disadvantage that it needs a power supply voltage of at least two gate/source threshold voltages to operate.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide an integrated circuit with a memory and a current sense amplifier that operates down to lower supply voltages.
The integrated circuit according to the invention is described in claim
1
. In the sense amplifier the gate/source voltage drop of the load transistors is inserted in a direction opposite to the direction of the gate source voltage drop of the input transistors. Thus, the voltage drop from the inputs of the sense amplifier to the common node of the load transistors is the difference of the gate-source voltage drops of an input transistor and a load transistor, instead of a sum as in the prior art. As in the prior art, the cross coupling ensures that the voltage drop from the inputs of the sense amplifier to the common point are equalized. But because these voltage drops between the inputs and the common node are now smaller than in the prior art, a lower supply voltage suffices.
Usually, complementary outputs of a memory cell will be coupled to respective ones of the memory bit-lines; a whole column of memory cells may be connected to the bit-lines in this way, memory selection signals determining which memory cell will be able to affect current through the bit lines. However, one may also use a memory cell with single ended outputs. In that case, one of the bit-lines is coupled to the memory cell and the other bitline may be connected to a reference current source (dummy cell).
In an embodiment of the integrated circuit according to the invention the input transistors and the load transistors are all of the same conductivity type. Thus, the gate-source voltage drops of load transistors and input transistors can easily be made equal by passing the same currents through these transistors.
In another embodiment of the integrated circuit according to the invention the common node is connected to the same power supply connection as the bit lines, via a common current source. Thus, changes in current through the channel of one load transistor will force opposite changes in current through the other load transistor.
In another embodiment the drains of the input transistors are connected to a second power supply connection via a first and second current source respectively. Thus, changes in current through the drains of the input transistors force opposite changes in current through the channels of the load transistors to which these drains are connected. This will make the voltage drops between the inputs and the common node follow each other more closely. Preferably, the first and second current source are switchable, so that they can be switched off if reading from the memory is disabled. More preferably, the first and second current source each comprise a switch for pulling the potential on the drain of the input transistors to the potential of the power supply to which the bit lines are connected. This switches the sense amplifier off more quickly and prevents floating nodes.
REFERENCES:
patent: 4766333 (1988-08-01), Mobley
patent: 4771194 (1988-09-01), Van Zeghbroeck
patent: 5253137 (1993-10-01), Seevinck
Bellefroid Lodewijk P.
Seevinck Evert
Segaar Rene
Le Thong
Nelms David
U.S. Philips Corporation
Wieghaus Brian J.
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