Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-03
2006-10-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07117457
ABSTRACT:
This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that only temporally mutually exclusive currents, or currents whose cumulative sum is less than a predetermined value, can flow in any given switch cell. Techniques for current event merging and current event culling, and techniques for handling timing and current variances may be used.
REFERENCES:
patent: 6794614 (2004-09-01), Taniguchi et al.
patent: 6832361 (2004-12-01), Cohn et al.
patent: 6850103 (2005-02-01), Ikeno et al.
patent: 7007256 (2006-02-01), Sarkar et al.
patent: 2003/0212538 (2003-11-01), Lin et al.
Doan Nghia M.
Kwok Edward C.
MacPherson Kwok & Chen & Heid LLP
Sequence Design, Inc.
Siek Vuthe
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