Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2011-03-08
2011-03-08
Eisen, Alexander (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S077000, C315S169300
Reexamination Certificate
active
07903053
ABSTRACT:
A matrix display apparatus includes a plurality of current-driven display devices arranged along row and column directions, a first circuit provided for each of the display devices, a plurality of data lines arranged for each column, with the data lines supplying an image data signal to a plurality of pixel circuits included in each one of the columns, and a plurality of row scanning lines for transmitting a scanning signal for selecting row by row the plurality of pixel circuits. The first circuit includes a field effect transistor for supplying one of the display devices with a current, which has a control electrode and two principal electrodes, a first switch connecting the control electrode and one of the principal electrodes of the field effect transistor, and a second switch having one terminal connected to the one of the principal electrodes of the field effect transistor and having another terminal connected to one of the data lines along the column of the first circuit. The first circuits in the column are connected in successively divided manner to the plurality of the data lines through the second switch.
REFERENCES:
patent: 6667580 (2003-12-01), Kim et al.
patent: 6686699 (2004-02-01), Yumoto
patent: 6839057 (2005-01-01), Iguchi
patent: 6975290 (2005-12-01), Asano
patent: 6989826 (2006-01-01), Kasai
patent: 7071911 (2006-07-01), Inukai
patent: 7106281 (2006-09-01), Kim et al.
patent: 7199775 (2007-04-01), Igarashi et al.
patent: 7310092 (2007-12-01), Imamura
patent: 7348947 (2008-03-01), Inukai
patent: 7425937 (2008-09-01), Inukai
patent: 7425939 (2008-09-01), Asano
patent: 7489290 (2009-02-01), Shin
patent: 7501999 (2009-03-01), Shin
patent: 7742021 (2010-06-01), Shin
patent: 2002/0118150 (2002-08-01), Kwon
patent: 2003/0128200 (2003-07-01), Yumoto
patent: 2004/0113873 (2004-06-01), Shirasaki et al.
patent: 2004/0183752 (2004-09-01), Kawasaki et al.
patent: 2004/0207578 (2004-10-01), Koyama
patent: 2005/0007359 (2005-01-01), Iseki et al.
patent: 2005/0104815 (2005-05-01), Komiya et al.
patent: 2005/0122150 (2005-06-01), Iseki et al.
patent: 2005/0174307 (2005-08-01), Nishitoba et al.
patent: 2005/0285151 (2005-12-01), Kawasaki
patent: 2006/0114194 (2006-06-01), Kawasaki et al.
patent: 2006/0114195 (2006-06-01), Yamashita et al.
patent: 2008/0062093 (2008-03-01), Imamura
patent: 2003-050564 (2003-02-01), None
patent: 2003-076327 (2003-03-01), None
patent: 2004-004789 (2004-01-01), None
patent: WO 2004/097787 (2004-11-01), None
Iseki Masami
Kawano Fujio
Kawasaki Somei
Yamashita Takanori
Canon Kabushiki Kaisha
Eisen Alexander
Fitzpatrick ,Cella, Harper & Scinto
Mandeville Jason M
LandOfFree
Current programming apparatus, matrix display apparatus and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current programming apparatus, matrix display apparatus and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current programming apparatus, matrix display apparatus and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2703708