Electronic digital logic circuitry – Having logic levels conveyed by signal frequency or phase
Reexamination Certificate
2000-09-25
2002-12-10
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Having logic levels conveyed by signal frequency or phase
C326S093000, C326S094000
Reexamination Certificate
active
06492840
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This patent relates to current-mode logic (CML) circuitry and more specifically to a new low-voltage, high-speed gate family consisting of both OR/NOR and AND/NAND logic functions, as well as other more complex functions. These logic gates are needed in many high speed applications where operation in the GHz range is required, such as in products which address the rapidly growing wireless and portable markets.
BACKGROUND OF THE INVENTION
Brief Description of the Prior Art
Current mode logic (CML) or emitter coupled logic (ECL) circuits are commonly used in high speed applications operating in the GHz frequency range. In these circuits, to reduce the storage time, caused by the presence of minority carriers, the transistors are usually not allowed to operate in hard saturation. Storage time, which is the time before an on transistor starts to turn off, tends to decrease the speed of the circuit. In CML circuits a constant current is maintained in the emitter legs of the transistors with current switching from one transistor leg to another depending on the states of the input signals.
FIG. 1
(prior art) shows one version of a conventional OR/NOR gate implemented in MOS CML. The circuit is made up of stacked transistors pairs 3-4 and 5-6 which allows for differential inputs A/{overscore (A)} and B/{overscore (B)} to be applied, respectively. Current source
7
maintains a constant current I through the legs of the circuit at all times. There are three paths, one of which will always be enabled, for current to flow through the circuit, as follows: a) through resistor
1
and transistors
3
and
5
, b) through resistor
1
and transistor
6
, and c) through resistor
2
and transistors
4
and
5
. In the circuit, the signals at A/{overscore (A)} have to operate with a DC voltage shift relative to the signals at B/{overscore (B)}. For very low V
DD
voltages there is limited headroom available for this voltage shift in order to maintain proper drain-to-source voltage, V
ds
, across the transistors and this usually limits the number of complementary inputs to two. One way to accomplish this voltage shift is with the use of source followers but these add complexity and tend to slow down the circuit. This circuit provides both OR (A+B) and it's complementary NOR ({overscore (A+B)}) outputs. A truth table for the circuit is included below.
OR
NOR
A
B
A + B
{overscore (A + B)}
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
0
Here the difference between a logic 0 and logic 1 is small, on the order of 400 to 800 mVolts. Some drawbacks of the circuit include:
1. Not suitable for ultra-low voltage operation of <1.2 volts due to the circuit's limited headroom for V
ds
across the stacked transistors pairs.
2. Limited to two inputs, A/{overscore (A)} and B/{overscore (B)}.
3. Signals B and {overscore (B)} have to be DC shifted compared to signals A and {overscore (A)}.
Although this gate is inherently fast, the required level shifting circuitry, not shown, tends to slow the overall operation of the circuit.
FIG. 2
(prior art) shows another commonly used CML circuit which overcomes the problems of the circuit in
FIG. 1
, but as will be discussed, has its own set of problems. Singled-ended input signals A and B are inserted at the gates of transistors
10
and
11
. Resistor
8
connects the drains of transistors
10
and
11
to V
DD
to provide a path for current to flow into current source
13
when either or both of these inputs are high (logic level 1). This circuit is not limited to two inputs, although only two are shown, and overcomes the DC level shifting problem of the previous circuit by operating all the transistors at the same voltage level. In addition, transistor
12
and resistor
9
are used to provide another path for current I to flow into current source
13
when both of the input transistors
10
and
11
are OFF. The V
ref
input is a DC level which biases transistor
12
at the mid-point of the A and B input signal's voltage swing. If both A and B inputs are low (logic level 0), all the current I will flow through V
ref
transistor
12
. Then as inputs A and/or B turn on (logic level 1) current will switch and flow through transistors
10
and/or
11
. As with the previous circuit, both OR (A+B) and it's complementary NOR ({overscore (A+B)}) outputs are generated. Although this circuit does overcome the problems of the previous circuit, it has its own drawbacks, as follows:
1. A reference voltage at mid-signal is required.
2. The circuit only allows single-ended inputs which usually implies larger input swings. This in turn can increase the voltage supply size and reduces the circuit speed. An alternative sometimes used is to keep the input swing constant and increase the size of the MOS transistors, but this also negatively impacts the circuit speed.
3. Less immunity to noise due to single-ended operation.
4. Circuit delay is more sensitive to the parasitic elements at node N
1
since the node has more movement with V
ref
remaining constant while the inputs A and B move.
SUMMARY OF THE INVENTION
There is a rapidly growing need in the wireless and portable markets, as well as other markets, for ultra low-power/low-voltage circuitry. High-speed logic circuits operating in the GHz range are more and more in demand. Emitter coupled logic (ECL) circuits represent one family that has been extensively used in wireless applications such as the phase lock loop (PLL) in prescalers and optical communication systems. And more recently CMOS current mode logic is becoming prevalent in the GHz domain.
This invention describes a new family of current mode logic (CML) gates which includes OR/NOR, AND/NAND gates, and other more complex functions, all of which use a complementary feedback signal to drive the gate of the V
ref
transistor
12
(
FIG. 2
) rather than a DC voltage often found in more conventional CML gate circuits. As a result of this feedback, the circuit operates in a pseudo differential manner although it uses only single-ended inputs. Because of this feedback aspect, the circuit has been called feedback current mode logic circuit or FCML. This circuit has both the advantages of the circuit of FIG.
2
and overcomes its drawbacks. The circuit switches current, controlled by a constant current source, between the input transistors and the complementary controlled transistor and can be configured with multiple inputs by adding additional transistors in parallel.
The new CML gate family described in this patent can be applied to CMOS, bipolar, BiCMOS, and other technologies today and will be adaptable to future technologies as well. As mentioned earlier, this family of gates eliminates several of the problems associated with conventional circuits of this type and offers its own advantages, as follows:
1. Suitable for low and ultra-low voltage operation.
2. Operates in a pseudo-differential manner.
3. Speed is less sensitive to parasitic elements associated with the circuit at the common source in a typical CMOS implementation.
4. Does not require a reference voltage needed in the conventional circuit of FIG.
2
.
5. Has good noise margins.
REFERENCES:
patent: 4590392 (1986-05-01), Vu
patent: 5055800 (1991-10-01), Black et al.
patent: 5077764 (1991-12-01), Yamashita
patent: 5373203 (1994-12-01), Nicholes et al.
patent: 5499280 (1996-03-01), Wilson et al.
patent: 5557649 (1996-09-01), Scheckel et al.
patent: 5581214 (1996-12-01), Iga
patent: 5945848 (1999-08-01), Ali
patent: 6157693 (2000-12-01), Jayaraman
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
Tran Anh
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