Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-09-03
2004-07-13
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S087000
Reexamination Certificate
active
06762624
ABSTRACT:
BACKGROUND
The majority of logic circuitry that is built today with CMOS technology is designed with rail-to-rail logic, in which all switching paths between the supply and ground are connected serially with complementary NFET (n-type field effect transistor) and PFET (p-type field effect transistor) devices. In the static state, no current is drawn in rail-to-rail logic circuitry because either the PFET or the NFET devices are turned off. Current is only needed during transitions. Thus, power is dissipated proportionally with the transition frequency (or clock speed).
For circuits requiring minimal supply bounce at the V
dd
and ground rails, as well as maximum isolation, voltage ripples arising from current spikes during the transitions of the traditional rail-to-rail CMOS logic family must be carefully suppressed. As clock speeds exceed multi-gigabit rates, this problem gets much harder to control. In these operating environments, an alternative logic family, known as CML (current mode logic), typically is used. In the CML logic family, a constant current always is present for each switch. The steering of this current generates a differential voltage that corresponds to logic 1 or logic 0. The CML logic family reduces current spikes, but requires power consumption regardless of clock speed or logic transitions.
Referring to
FIG. 1
, a traditional CML logic buffer
10
consists of a differential pair of transistors
12
,
14
, load resistors
16
,
18
, and a current source
20
that feeds the sources of the differential transistor pair. Additional stacks of differential pairs may be inserted into the logic tree to merge logic. For example, as shown in
FIG. 2
, three differential pairs may be used to form a latch
22
. Referring to
FIG. 3
, the bias current for a CML current source typically is provided by a master reference current source
24
feeding a reference current (I
ref
) into a diode-configured NFET current mirror
26
. The master current (I
ref
) is derived from a voltage-to-current (V-I) converter using a source of a constant voltage (V
ref
), which may be derived from a band-gap voltage reference, and a resistor (R). The resistor may match the load resistor of a CML gate, or it may be an external or laser trimmed precision resistor if constant current is desired.
The speed of a CML logic cell depends on the RC time constants at the load resistors, as well as the switching speed of the FET differential pair switches. During manufacture, the value of the load resistance is selected first. Then, the value of current source is selected by device size to achieve an acceptable voltage swing across the load resistors. The voltage swing typically corresponds to the voltage needed to switch the next CML logic gate.
For a CML circuit to meet timing requirements in a large volume manufacturing environment, the speed of the CML gates must be designed for the slowest corner case, which typically corresponds to the slowest FET devices, the highest load resistor tolerance that is guaranteed by the IC process, the highest temperature, and lowest V
dd
required. With this requirement fulfilled, the same design must be specified and guaranteed for its maximum power consumption under its worst case condition, which typically corresponds to the fastest FET devices and lowest load resistor tolerance of the IC process, and the highest temperature and highest V
dd
required by the product. Since minimal power dissipation translates directly into lower packaging costs and higher reliability, low power consumption is a major competitive advantage of a given circuit design. Presently, the maximum power dissipated by the CML logic family is dictated by the current required for the slow case corner.
SUMMARY
In one aspect, the invention features a circuit system that includes a logic circuit and a bias circuit. The logic circuit includes one or more current mode logic gates each of which is operable to steer a respective tail current to produce an output voltage swing. The bias circuit is operable to maintain the voltage swing of each current mode logic gate independent of changes in tail current level.
In another aspect, the invention features a circuit system that includes a logic circuit and a switching speed reference circuit. The logic circuit includes one or more current mode logic gates each of which is operable to steer a respective tail current to produce an output voltage swing. The switching speed reference circuit is operable to detect intrinsic switching speeds of the one or more current mode logic gates.
In another aspect, the invention features a circuit system that includes a logic circuit and a tail current adjustment circuit. The logic circuit includes one or more current mode logic gates each of which is operable to steer a respective tail current to produce an output voltage swing. The tail current adjustment circuit is operable to dynamically adjust the current mode logic gate tail currents to maintain logic gate switching speed in correlation with a reference clock frequency.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.
REFERENCES:
patent: 4145623 (1979-03-01), Doucette
patent: 5889431 (1999-03-01), Csanky
patent: 5909127 (1999-06-01), Pearson et al.
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 6222386 (2001-04-01), Alford et al.
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