Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Parallel controlled paths
Reexamination Certificate
2003-08-29
2004-08-10
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Parallel controlled paths
C327S108000, C455S218000
Reexamination Certificate
active
06774700
ABSTRACT:
BACKGROUND OF THE INVENTION
Several modern high-speed serial data busses, normally used for digital communication between physically separated electronic devices, implement the well-known, time-tested “differential pair” signal line configuration to transmit and receive data. The differential pair typically consists of two signal lines, a positive (“p”) signal line and a negative (“n”) signal line, which normally exhibit one of two possible voltage values during normal data transmission. During such data transmission, the two signal lines exhibit different voltage values from each other. For example, a data value of ‘1’ is usually indicated on a differential pair with a voltage V+ on the “p” line, and a lower voltage V− on the “n” line. Similarly, to indicate a data value of ‘0’, the “p” line holds a voltage of V− while the “n” line exhibits a voltage of V+. Therefore, except during times in which the data value of the differential pair is in transition, the magnitude of the differential voltage between the two signal wires generally remains at about V+ minus V−. Advantageously, differential pair signal lines have long been known to demonstrate high common-mode rejection, which allows the data being transferred to be unaffected by noise that is induced onto both signal wires of the differential pair.
In addition to transferring data, the modern serial data busses that utilize differential pairs for data transfer, such as Serial AT Attachment (Serial ATA), also utilize those same signal wires to indicate changes in the overall state of the communication link, such as to invoke data bus power management. To indicate these state changes, the two signal wires of the differential pair normally are driven so that the resulting differential voltage is substantially zero for specific periods of time. Driving the differential signal pair in this manner is commonly known as “squelch,” or “out-of-band” signaling. As a result, electronic devices connected to such a bus are usually required to generate the squelch state of the differential pair, which generally lasts only for a few tens or hundreds of nanoseconds.
Due to the high-speed nature of modern serial data busses employing a differential signal pair, one attractive logic technology for implementing a transmission circuit for such an interface is current-mode logic (CML). Discrete CML components have become more readily available and popular due to their improved power-delay product and back-termination capability in comparison to their more widely recognized emitter-coupled logic (ECL) counterparts. Additionally, CML components are easily adapted to support a variety of voltage swing levels normally used for differential pair signal lines.
Given the potential benefits associated with the use of CML in this environment, a need presently exists for a reliable CML differential signal generation circuit that also produces a squelch state. Such a circuit would take advantage of the high-speed, low-power, variable voltage characteristics of CML while also generating a squelch state over the same differential pair in a reliable fashion.
SUMMARY OF THE INVENTION
Embodiments of the invention, to be discussed in detail below, provide an electrical circuit for generating a differential data signal and a squelch state over a differential signal pair having a positive (‘p’) and a negative (‘n’) signal line. A current-mode logic (CML) buffer having both true and complementary data outputs drives the ‘p’ and ‘n’ lines of the differential signal pair, transferring the data embodied in the data signal driving the input of the buffer. In addition, a CML multiplexer also has true and complementary data outputs which are coupled to the corresponding outputs of the buffer. The data inputs of the multiplexer are driven by the data signal and the logical inversion of the data signal. Additionally, a squelch state signal drives the selector input of the multiplexer so that the squelch state appears on the differential signal pair when the squelch state signal is active.
Use of embodiments of the invention result in a simple circuit that enjoys the various benefits of CML technology as applied to high-speed data transmission while also providing a straightforward means of forcing a squelch state over the differential signal pair.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5796301 (1998-08-01), Tanabe et al.
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6353338 (2002-03-01), Fiedler et al.
patent: 2003/0081743 (2003-05-01), Chiang et al.
patent: 2003/0148801 (2003-08-01), Deyring et al.
Agilent Technologie,s Inc.
Nguyen Minh
Way Kyle J.
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