Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-15
2004-02-24
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S298000, C257S329000, C257S300000, C365S185240
Reexamination Certificate
active
06696713
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-181918, filed Jun. 16, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a cell transfer transistor of a DRAM, in particular, to a semiconductor memory provided with a vertical transistor and the method of manufacturing the same.
In the case of a cell transfer gate transistor of a DRAM having a stacked capacitor, in conformity with the miniaturization of the design rule, it is required to reduce the gate length in a manner equivalent to the minimum design rule. On this occasion, the threshold value of the cell transfer transistor is required to be kept substantially constant in view of the leak current to be generated when the transistor is in the state of OFF. On the other hand, in order to enable the threshold value of the cell transfer transistor to be kept constant, the concentration of the channel region impurity is required to be increased taking the short channel effects thereof into consideration. However, when the concentration of the channel region impurity is increased, it will lead to an increase of junction leak as well as to the deterioration of pose characteristics.
It is necessary, in order to suppress these phenomena, to employ a vertical transistor in place of the conventional planar transistor, thereby separating the gate length of the cell transfer transistor away from the minimum design rule. As one example of the vertical transistor, there is proposed “A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAM” which is set forth on pages 23 through 26 of International Electron Device Meeting (IEDM) 1989 Technical Digest.
However, the memory cell constituted by the conventional vertical transistor has been manufactured in such a way that a silicon substrate is etched to form silicon columns, and transfer gates are formed around this silicon column. As a result, the manufacturing process thereof is relatively complicated, thus increasing the manufacturing cost thereof.
BRIEF SUMMARY OF THE INVENTION
The present inventor has been accomplished in view of the aforementioned problems, and therefore, an object of this invention is to provide a semiconductor memory which is simply manufactured, and can be manufactured at low cost. Another object of this invention is to provide a method of manufacturing such a semiconductor memory.
Namely, according to a first aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the monocrystalline silicon layer being contacted with the first diffusion region;
a second diffusion region of a first conductivity type, which is formed on a surface of the monocrystalline silicon layer; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
According to a second aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a first monocrystalline silicon layer of a first conductivity type which is located between the electrodes, opposite sidewalls of the first monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the first monocrystalline silicon layer being contacted with the first diffusion region;
a second monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the second monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the second monocrystalline silicon layer being contacted with the first diffusion region and with the element isolation region;
a second diffusion region of a first conductivity type, which is formed on a surface of each of the first and second monocrystalline silicon layers; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
According to a third aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a third diffusion region of a second conductivity type, which is formed on a surface of the element region, the third diffusion region being contacted with the first diffusion region and with the element isolation region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a first monocrystalline silicon layer of a first conductivity type which is located between the electrodes, opposite sidewalls of the first monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the first monocrystalline silicon layer being contacted with the first diffusion region;
a second monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the second monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the second monocrystalline silicon layer being contacted with the first diffusion region and with the third diffusion region;
a second diffusion region of a first conductivity type, which is formed on a surface of each of the first and second monocrystalline silicon layers; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
It is preferable, with semiconductor memories according to the aforementioned first and third aspects of this invention, to dispose the bottom face of the second diffusion region at a place which is lower than the bottom face of the insulating film.
In the semiconductor memory according to the first aspect of this invention, it may further comprise a storage node contact connected electrically with the second diffusion region; a capacitor connected electrically with the storage node contact; a bit line contact connected electrically with a portion of the second diffusion region other than the portion thereof which is electrically connected with the storage node contact; and a bit line connected electrically with the bit line contact.
On the other hand, in the semiconductor memory according to each of the second and third aspects of this invention, it may further comprise a storage node contact connected electrically with the second diffusion region formed on the surface of the second monocrystalline silicon layer; a capacitor connect
Banner & Witcoff , Ltd.
Eckert George
Kabushiki Kaisha Toshiba
Nguyen Joseph
LandOfFree
Semiconductor memory provided with vertical transistor and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory provided with vertical transistor and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory provided with vertical transistor and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3299665