Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-08-28
2003-09-09
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C326S086000
Reexamination Certificate
active
06618786
ABSTRACT:
TECHNICAL FIELD
The disclosure below relates to current-mode bus line drivers and to methods of achieving relatively constant current output such bus line drivers.
BACKGROUND OF THE INVENTION
Current-mode signaling is ideal for certain situations, such as a bus-based signaling environment. When using current-mode signaling in this environment, an active driver device alternately drives either a high current or a low current on the bus. The current passes through the impedance of the bus line and any termination resistance, thereby producing corresponding voltages on the bus line. Generally, only one driver is active at any given time, and presents a high impedance to the bus when it is not active. However, drivers used in high-speed bus lines are sometime active during overlapping times to enable higher signaling rates.
FIGS. 1-4
illustrate one bus design where two devices might be concurrently active. In this design, there is a single bus line
20
having a fixed impedance. In this example, the bus line impedance is 28 ohms. The bus is terminated at one end with a termination resistance R
term
which is approximately equal to the bus line impedance of 28 ohms. This end of the bus line is referred to herein as the distal end. The bus is biased by a termination voltage V
term
, which in this example is equal to 1.8 V.
A plurality of driver devices
22
-
25
are connected to alternately drive bus line
20
. In addition, a signal receiving device
26
is connected to receive and interpret bus line signals resulting from the activities of driver devices
22
-
25
. The signal receiving device is located at a first or proximal end of the bus line in this example. The signal receiving device presents a high impedance to the bus line.
FIGS. 2-4
illustrate waveforms that result when driver device
23
transitions from a “high” bus line voltage to a “low” bus line voltage. In this example, the high bus voltage V
hi
is equal to 1.8 volts, and the low bus voltage V
lo
, is equal to 1.0 volts. To produce V
hi
on the bus, driver device
23
supplies no current to the bus. To produce V
lo
, driver device
23
sinks 30 mA.
FIG. 2
shows the current waveform at driver device
23
as it transitions from V
hi
to V
lo
. Initially, the current is zero, resulting in a bus voltage of V
hi
. When driver device
23
switches to produce a “low” bus voltage of V
lo
, the current through the driver device is −30 mA.
FIG. 3
shows the resulting voltage waveform at driver device
23
. Initially, at the transition of driver device
23
from 0 to 30 mA, driver device
23
sees an impedance of 28 ohms in each bus line direction. These two impedances are seen in parallel, so the overall impedance is equal to 1/(1/28+1/28) or 14 ohms. The voltage drop across this impedance is equal to impedance multiplied by current, or −30 mA×14 ohms (about −400 mV). The bus line is biased at its distal end by 1.8 V, so the resulting voltage at driver device
23
is 1.8 V−400 mV=1.4 V. This voltage level (1.4 V) is referred to as intermediate voltage V
int
in FIG.
3
. Generally, V
int
is equal to (V
hi
+V
lo
)/2.
This 400 mV voltage signal propagates in each direction on the bus line, at a finite velocity. When the signal gets to the distal end of the bus line, it encounters the matched impedance of R
term
, and there is no signal reflection. When the signal gets to the proximal end of the bus, however, it encounters the infinite input impedance of signal receiving device
26
. This causes a voltage reflection, creating a return voltage wave whose amplitude is equal to the voltage of the original −400 mV signal. This voltage subtracts from the existing bus line voltage of 1.4 V, to result in a bus line voltage of V
lo
, or 1.0 V in the illustrated example.
FIG. 4
shows the resulting voltage waveform at signal receiving device
26
. The signal receiving device sees a single transition from V
hi
to V
lo
, delayed in time by the propagation delay from driver device
23
to signal receiving device
26
.
This second −400 mV signal propagates all the way back to the distal end of the bus line. When the second reflection reaches driver device
23
, the driver device sees the full 800 mV signal. This 800 mV signal continues back towards R
term
, which absorbs the signal and eliminates any further reflections.
FIG. 3
shows the arrival of this second signal or wavefront at driver device
23
, at which time the voltage becomes equal to V
lo
.
At this point, the circuit has reached a steady state voltage of V
lo
, (1.0 V) and no steady-state current flows through the proximal end of the signal line. As a result, the total bus line impedance seen by driver device
23
is now the impedance of the distal side of the bus line: 28 ohms. This is what produces the steady-state output voltage of 1.0 V: V
term
−30 mA×R
bus
=1.0 V.
When it is desired to operate the bus line at the highest possible speeds, subsequent signal transitions are introduced on the bus line before the signal from the earlier transitions have reached their final, steady state. Although this creates complex waveforms at the driving devices, the signal at the signal receiving device remains relatively simple, so that the signal receiving device can interpret the signal by differentiating only between two signal voltages: V
hi
and V
lo
.
However, the situation becomes slightly more complicated in the case of so-called “back-to-back” reads from driver devices. A back-to-back read is when a first driver device produces a signal that is immediately followed by a signal from a second driver device. Because of signal propagation delays, this has the potential of creating signal glitches, sometimes referred to as “wired-OR glitches.”
Consider the example shown in
FIG. 5
where the bus configuration includes a signal receiving device
40
, a first and proximal driver device
41
, and a second and distal driver device
42
. In this example, t
d
represents the signal propagation delay between distal driver device
42
and proximal driver device
41
. The symbol t
r
represents the signal propagation delay between proximal driver device
41
and signal receiving device
40
.
Assume that proximal driver device
41
produces a low voltage signal, which is immediately followed by a low voltage signal from device driver
42
. One way to accomplish this is to turn off proximal driver device
41
simultaneously with turning on driver device
42
. Because of signal propagation delays, however, this would result in a voltage glitch at signal receiving device
40
: the terminating signal from device
41
would reach signal receiving device
40
before the new signal from device
42
arrived. In other words, it would appear that the bus was not being driven for some short period of time.
While a glitch such as this could perhaps be accommodated, doing so would not utilize the full bandwidth of the bus line. To utilize the full bandwidth, distal driver device
42
is turned on for some time prior to turning off proximal driver device
41
, so that its signal reaches signal receiving device
40
at the same time as the trailing edge of the signal from proximal driver device
41
.
FIGS. 6-8
illustrate this sequence.
FIG. 6
shows the current waveforms at distal driver device
41
and proximal driver device
42
, respectively. At point A, the distal driver device
42
is turned on and begins sinking 30 mA. At a later time B, the proximal driver device
42
is turned off and stops sinking current. The time from A to B is equal to t
d
.
FIG. 7
shows the resulting voltage at distal driver device
42
. At point A, when distal driver device
42
is turned on, the bus is presented with an additional current of 30 mA. Initially, this current sees an effective resistance of 14 ohms. The additional voltage drop caused by this current is equal to the original bus line voltage of 400 mV. The total voltage drop on the bus signal line is the sum of the voltage drop caused by proximal driver device
41
and the voltage
Li Yingxuan
Sidiropoulos Stefanos
Lee & Hayes PLLC
Rambus Inc.
Thai Xuan M.
Vo Tim
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