Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-04-07
2001-08-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06275066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bidirectional input/output buffer, and more particularly, to a bidirectional input/output buffer for impedance matching, which allows data to be simultaneously sent and received over a single transmission line between two chips in a current-mode.
2. Description of the Related Art
As processes for fabricating integrated circuits improve, the performance of systems for achieving high speed operation may be significantly limited by the data transmission speed between chips. A bidirectional input/output buffer, a type of input/output buffer for data transmission, simultaneously sends and receives data over a single cable so that transmission performance of each single cable is doubled, and recovers only the received signals from the outside.
FIG. 1
is a schematic diagram showing the structure of a signal transmission system of a conventional bidirectional input/output buffer circuit. Bidirectional input/output buffers are respectively provided in chips
100
A and
100
B for transmission of data between the two chips
100
A and
100
B which are coupled to a transmission line having an impedance Z
0
in FIG.
1
. The bidirectional input/output buffers include; transmitting terminals to which transmission signals IN
1
and IN
2
, to be sent to other chips, are applied; input/output nodes OUT
1
and OUT
2
through which signal voltages are sent to other chips and signal voltages from the other chips are received; recovering terminals RET
1
arid RET
2
at which the received signals from other chips have recovered original values; reference voltage generators
103
a
and
103
b
for respectively generating reference voltages Vref
1
and Vref
2
which are selected according to voltages of the transmission signals IN
1
and IN
2
and which are respectively compared with voltage values of the input/output nodes OUT
1
and OUT
2
each having a voltage value in which the signal to be transmitted outwardly and the signal received from the outside are mixed, to recover the signals received from the outside in the two chips
100
A and
100
B; output buffers
101
a
and
101
b
for respectively buffering the transmission signals IN
1
and IN
2
; and voltage comparators
102
a
and
102
b
for comparing the reference voltages from the reference voltage generators
103
a
and
103
b
with the voltages of the input/output nodes OUT
1
and OUT
2
respectively.
In the operation of the signal transmission system of
FIG. 1
, voltages applied to the input/output nodes OUT
1
and OUT
2
according to the transmission signal IN
1
to be outwardly transmitted and the signal IN
2
received from the outside in one chip
100
A, appear to be the average value of signal voltages transmitted by the two chips
100
A and
100
B. At this time, assuming that the voltage values transmitted between the two chips
100
A and
100
B are classified into only two levels, 0 volts and a high level voltage having a predetermined value, the input/output node OUT
1
has a high level voltage, a ½ high level voltage or 0. The voltages of the input/output nodes OUT
1
and OUT
2
are respectively compared with the reference values Vref
1
and Vref
2
which are generated by the reference voltage generators
103
a
and
103
b
according to the transmission signals IN
1
and IN
2
, to provide original signal levels. Table 1 shows the reference voltages Vref
1
and Vref
2
, which depend on the voltage values of the transmission signals IN
1
and IN
2
, and signal values recovered from the level values of the input/output nodes OUT
1
and OUT
2
at the recovering terminals RET
1
and RET
2
in the conventional, bidirectional input/output buffers.
TABLE 1
IN1
High
High
Low
Low
IN2
High
Low
High
Low
OUT1, OUT2
VDD
0.5 VDD
0.5 VDD
0
Vref1
0.75 VDD
0.75 VDD
0.25 VDD
0.25 VDD
Vref2
0.75 VDD
0.25 VDD
0.75 VDD
0.25 VDD
RET1
High
Low
High
Low
RET2
High
High
Low
Low
It can be known from Table 1 that the transmission signals IN
1
and IN
2
are respectively transmitted to the corresponding recovering terminals RET
2
and RET
1
of the other chips at the same level value. However, since conventional bidirectional input/output buffers operate in a voltage-mode, full voltage swing appears at nodes which have capacitor components in the circuits of the bidirectional input/output buffers. In this situation, switching speed is slowed down, which causes the transmission speed of the bidirectional buffer to be limited.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a current-mode bidirectional input/output buffer which can perform impedance matching in which an impedance has a stable characteristic in spite of variations in processes for fabricating chips, for achieving high rate data transmission between the chips.
To achieve the object of the present invention, there is provided a current-mode bidirectional input/output buffer which communicates signals with an external chip having the same current-mode bidirectional input/output buffer. The current-mode bidirectional input/output buffer includes a transmitting-receiving average voltage output unit for converting an average current value between a transmission signal to be transmitted to the external chip and a receiving signal transmitted from the external chip, into an average voltage; a reference voltage output unit for converting a predetermined reference current value selectively generated according to a voltage level of the transmission signal, into a reference voltage; a comparator for comparing the voltage from the transmitting-receiving average voltage output unit with the voltage from the reference voltage output unit to provide a logic signal corresponding to the received signal transmitted from the external chip; and a bias voltage generator for generating a bias voltage such that the impedance of each output unit is matched with a characteristic impedance of a transmission line coupled to the external chip, and for providing the bias voltage to the transmitting-receiving average voltage output unit and the reference voltage output unit.
The current-mode bidirectional input/output buffer also includes a CMOS level converter for converting the output of the comparator into a CMOS level.
In the bias voltage generator, first and third PMOS transistors are coupled in serial between a power supply voltage VDD and a negative input terminal of a second operational amplifier; second and fourth PMOS transistors are coupled in serial between the power supply voltage VDD and a positive input terminal of the second operational amplifier; the output terminal of a first operational amplifier is coupled to gates of the first and second PMOS transistors in common; a positive input terminal of the first operational amplifier is coupled to the negative input terminal of the second operational amplifier and one end of an external resistor; the other end of the external resistor is coupled to ground; the output terminal of the second operational amplifier is coupled to the gate of a first NMOS transistor; and the drain and source of the first NMOS transistor are respectively coupled to the positive input terminal of the second operational amplifier and ground.
In the transmitting-receiving average voltage output unit, a first constant current source is coupled between the power supply voltage VDD, the anode of a first diode and the drain of a second NMOS transistor; an inverted transmission signal is applied to the gate of the second NMOS transistor, the cathode of the first diode is coupled to the transmission line of the external chip, the drain of a third NMOS transistor and the positive input terminal of the comparator; and the gate of the third NMOS transistor is coupled to the gate of the first NMOS transistor.
The first constant current source operates with each gate voltage of the second and fourth PMOS transistors as a bias voltage.
In the reference voltage output unit, a second constant current source and a switch unit for switchin
Park Hong-June
Sim Jae-Yoon
Le Don Phu
Leydig Voit & Mayer Ltd
Pohang University of Science and Technology Foundation
Tokar Michael
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