Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-07-28
2001-12-04
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S161000
Reexamination Certificate
active
06326914
ABSTRACT:
The present invention relates to an analog-to-digital converter. More particularly to an analog-to-digital converter to be used in telecommunication applications such as ASDL/NDSL UMTS/GPRS that require a very high resolution, high speed, a low power consumption, a low supply voltage, a small silicon area on the electronic chip, and preferably at low cost.
Analog-to-digital converters [ADC] are generally known in the art, e.g. from the article “An Embedded 240mW 10-b 50-MS/s CMOS ADC in 1-mm
2
” by K. Bult et al. Therein is disclosed an averaging “flash” analog-to-digital converter. The flash architecture allows achieving a fast analog-to-digital [A/D] conversion that is performed in voltage mode, i.e. by summing voltages. This requires a relatively high voltage supply, e.g. several batteries. Additionally, a large amount of very accurate and fast comparators is required. According to the article, the last problem is solved by “averaging” the converter and by reducing the total chip area by using the “folding” technique. The purpose of folding is to reduce the number of comparators by using each comparator more than once. Obviously, folding requires a relatively sophisticated digital control.
An object of the present invention is to provide an analog-to-digital converter of the above known type but adapted to operate at low voltage supplies.
According to the invention, this object is achieved due to the fact that the converter of the invention comprises a first set of first current cells coupled in parallel between a first current line and a second current line of a differential current bus, said lines carrying a balanced differential input current corresponding to a differential analog input signal of said converter, each first current cell of said set comprising first current source means adapted to supply a first additional current to said first and second current lines under control of first comparator means, the first comparator means of the first current cells of said first set are coupled in cascade, the first comparator means having first inputs coupled to said first and second current lines, second inputs coupled to outputs of first comparator means of a preceding first current cell in the cascade, and outputs coupled to second inputs of first comparator means of a next first current cell in the cascade.
In this way, The A/D conversion is realized in current mode instead of voltage mode. The power consumption is thereby reduced and the device is adapted to be used in battery operated products. The structure of the device is thereby also simplified because summing of currents is easier than summing of voltages. Indeed, operating in current mode is known to allow easy summing of signals by paralleling up the currents in a summing node. Furthermore, the present converter uses an Asynchronous Decision algorithm during the conversion of samples. Asynchronous logic is known in the art to be low power and high speed, e.g. compared to synchronous pipelined structures. The present converter can thus be seen as a Current Mode Asynchronous Decision A/D converter [CMAD].
Another characteristic feature of the present invention is that said converter comprises a second set of second current cells also coupled in parallel between said first and said second current lines of said differential current bus, each second current cell of said second set comprising second current source means adapted to supply a second additional current to said first and second current lines under control of second comparator means, the second comparator means of the second current cells of said second set are coupled in cascade, the second comparator means having first inputs coupled to said first and second current lines via respective amplifier means, second inputs coupled to outputs of second comparator means of a preceding second current cell in the cascade, and outputs coupled to second inputs of second comparator means of a next second current cell in the cascade, and that the second current cells of said second set are activated after the operation of the first current cells of said first set is completed.
In this way, the principle of “sub-ranging” the converter into two sets of current cells is applied. This reduces the amount of hardware, whereby the cost is also reduced owing to a smaller silicon area on the chip. For instance, if a “n”=12 bit digital word has to be obtained, the amount of hardware is reduced from 2
n
=2
12
to 2×2
n/2
=2×2
6
. This is a factor of 2
5
reduction of hardware.
A known problem of sub-ranging is that it is difficult to match the gain curve of the 2 sub-ranges in the A/D converter total dynamic range. The known prior art solution to this is an overlap of the sub-ranges and a digital correction afterwards. In the present invention, the 2 sub-ranges are summing up in the same current nodes, i.e. the first and the second lines of the differential current bus, so there is only one gain curve for the 2 sub-ranges and no need for overlap nor digital correction. Still the lower sub-range, i.e. the second set of second current cells, needs an additional gain of 2
n/2
=2
12/2
=2
6
=64. This additional gain is achieved by the amplifier means and is thus put in the digital decision path and not in the analog signal path. Therefore, the gain of 2
6
is not critical for the analog linearity of the A/D converter, as long as the gain tolerances stay within the comparator's hysteresis. The present A/D architecture is thereby robust towards technology and analog circuit tolerances.
The present invention is further characterized in that the operation of the first current cells of said first set is completed after a first half clock cycle, and in that, at the beginning of the second half of a clock cycle, a clock signal is applied to said second comparator means of at least the first second current cell in the cascade in order to activate the operation of the second current cells of said second set.
Also another characteristic feature of the present invention is that said converter comprises N−1 second sets of second current cells, said second sets operating in sequence, a second set being only activated after the operation of the second current cells of another second set is completed.
More generally, what is discussed above for a 2 sub-ranging may be extended to a N sub-ranging. The amount of hardware in then reduced from 2
n
to N×2
n/N
, where N is the number of sub-ranges, i.e. the first set of first current cells and the N−1 second sets of second current cells, and n the number of bits of the digital word. Clearly in this case, the N sub-ranges operate in N successive phases of the clock cycle.
A further characteristic of the present invention is that the first inputs of said second comparator means of the second current cells of said second set are connected to a first voltage line and a second voltage line forming together a voltage bus.
This increases the stability of the A/D converter and more particularly the accuracy of the second set(s) of second current cells thereof.
Yet another characteristic feature of the present invention is that said differential analog input signal is a differential voltage applied to control terminals of active devices of which the main path interconnects current sources with said first and second current lines, and that said first and second current lines are provided with impedance means adapted to convert said balanced differential input current flowing through the current lines into a differential voltage.
In this way, the device is adapted to operate with an input current as well as with an input voltage.
Another advantage of the present invention is that an accurate A/D conversion is obtained in a same technology, e.g. CMOS or BICMOS.
Further characteristic features of the present analog-to-digital converter [ADC] are mentioned in the appended claims.
The above and other objects and features of the invention will become more
Alcatel
Sughrue Mion Zinn Macpeak & Seas, PLLC
Wamsley Patrick
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