Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-06-22
2002-08-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S052000, C327S053000
Reexamination Certificate
active
06433590
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices and, more particularly to sense amplifier circuit of semiconductor memory devices.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional current mirror type sense amplifier circuit of semiconductor memory devices is illustrated. The sense amplifier is comprised of a reference voltage generating circuit
10
for generating a reference voltage, a sensing voltage generating circuit
20
for generating a sensing voltage, and a differential amplifier
30
for amplifying a difference voltage between the reference voltage and the sensing voltage.
A variable current sinker
29
has a current driving capability corresponding to the data state of a memory cell (not shown). That is, the variable current sinker
29
has current driving capability larger than that of a constant current sinker
19
when a memory cell stores a logic “0” (or logic “1”) data, but it has current driving capability smaller than that of the constant current sinker
19
when the memory cell stores a logic “1” (or logic “0”) data.
A sense amp enable signal {overscore (SA)} is externally applied to an input of a complementary metal oxide semiconductor (CMOS) inverter formed by a P-channel MOS (PMOS) transistor
11
and an N-channel MOS (NMOS) transistor
12
within the reference voltage generating circuit
10
. This signal {overscore (SA)} is also applied to an input of an inverter formed by a PMOS transistor
21
and an NMOS transistor
22
in the sensing voltage generating circuit
20
. NMOS precharge transistors
13
and
23
are provided for the voltage generating circuits
10
and
20
. These precharge transistors
13
and
23
has their gates externally applied with a precharge control signal &PHgr;PRE. Current mirror type PMOS transistors
14
and
24
are provided for the reference voltage generating circuit
10
and the sensing voltage generating circuit
20
, respectively. Between node N
2
and the dummy data line DDL, placed is an NMOS transistor
15
whose gate is coupled to an output (i.e., node N
1
) of the inverter formed by transistors
11
and
12
. Also, an NMOS transistor
25
is placed between the node N
5
and the main data line DL. Gate of the transistor
25
is coupled to an output (i.e., node N
4
) of the inverter formed by the transistors
21
and
22
. NMOS transistors
16
and
26
are further provided for the voltage generating circuit
10
and
20
, respectively.
The sense amplifier is enabled when the sense amp enable signal {overscore (SA)} changes from a logic high level to a logic low level. With the application of the low level signal {overscore (SA)}, PMOS transistors
11
and
21
are turned on, thus the voltage levels of the nodes N
1
and N
4
go high so as to make NMOS transistors
15
and
25
conductive. Thereafter, when the signal &PHgr;PRE goes high, the transistors
13
and
23
are turned on so that the voltage levels of nodes N
2
, N
3
, N
5
and N
6
(i.e., data lines DDL and DL) start to increase. The increase of the voltage levels of the nodes N
3
and N
6
are stopped at a point that respective current driving capacities of the PMOS transistors
11
and
21
balance with those of the NMOS transistors
16
and
26
.
After a given precharge period, the precharge control signal &PHgr;PRE becomes inactive low again and so the transistors
13
and
23
are rendered off. At this time, the transistors
14
and
24
deliver the same amount of current as sinks to the ground voltage Vss via the current sinker
19
so as to maintain the voltage level of node N
2
constant. This constant voltage is applied to the input IN
1
of the differential amplifier
30
as a reference voltage. Owing to the current mirror arrangement, the transistors
24
conducts the same current as the transistor
14
does. So, if the variable current sinker
29
has a current driving capability larger than that of the constant current sinker
19
, the sensing voltage level on node N
5
becomes lower than the reference voltage level on the node N
1
. On the contrary, if the variable current sinker
29
has a current driving capability smaller than that of the constant current sinker
19
, the sensing voltage of node N
5
becomes higher than the reference voltage on the node N
2
. These voltage differences are amplified by the differential amplifier
30
.
In general, the amount of current flowing through a MOS transistor is proportional to the gate-source voltage. NMOS transistors
13
and
23
have their sources coupled to the nodes N
2
and N
5
of different voltages, respectively, even though their drains and gates are applied with a constant voltage (i.e., power supply voltage) during a precharge period. Thus, the transistor
23
does not have the same current driving ability as the transistor
13
during the precharge period. Due to these differences in current, the voltage difference between the nodes N
2
and N
5
is not caused only by the difference between the current driving abilities of the current sinkers
19
and
29
. That is, when the variable current sinker
29
has current driving capability larger than that of the constant current sinker
19
during the precharge period, the node N
5
is expected to be pulled down faster than the node N
2
, but not because the node N
5
is lower than the node N
2
and so the transistor
23
conducts current larger than that of the transistor
13
; In addition, when the variable current sinker
29
has current driving capability smaller than that of the constant current sinker
19
during the precharge period, the node N
5
is expected to be pulled up faster than the node N
2
, but not because the node N
5
is higher than the node N
2
and so the transistor
23
conducts current smaller than that of the transistor
13
.
As described above, in case the transistors
13
and
23
cannot deliver the same current to the nodes N
2
and N
5
during a precharge period, (1) there may be a very small difference in the voltage levels of the nodes N
2
and N
5
, thereby reducing the data sensing speed and the sensing margin, (2) in the worst cases, the voltage levels of the nodes N
2
and N
5
may be reversed so that reading errors will occur.
To overcome such shortcomings, the use of the NMOS precharge transistors
13
and
23
should be restricted only to the early stage of precharging the data lines DDL and DL rapidly, and only the PMOS precharge transistors
14
and
24
having the same current driving capability must be devoted to the remaining stage of the precharge period that requires the precise precharge control.
In the above-described conventional sense amplifier circuit, the NMOS precharge transistors
13
and
23
are shut off compulsorily and abruptly by the external precharge control signal &PHgr;PRE. It is however not easy to control the inactivation timing of the precharge control signal &PHgr;PRE, and it is also desirable that the precharge transistors
13
and
23
are gradually shut off since such an abrupt shut-off will cause an unexpected transient in data sensing.
Moreover, as the precharge voltage levels on the nodes N
2
and N
5
increase during a precharge period, the source voltage levels of NMOS transistors
13
and
23
also increase and so their gate-source voltage decrease. Thus, NMOS transistors
13
and
23
, as well as PMOS transistors
14
and
24
, have their higher threshold voltages than expected due to the body effect (these threshold voltage variations due to the body effect can also be affected by the various process variations). As a result of this, the transistors
13
and
23
will shut off naturally before the discharge control signal &PHgr;PRE becomes inactive. Such a natural shut-off also appears in the PMOS transistors
14
and
24
having the same current driving ability owing to their current mirror arrangement so that the transistors
14
and
24
will shut off in worst case before the shut-off of NMOS transistors
13
and
23
that usually have different current driving abilities, thereby causing poor sensing performance
Im Heung-Soo
Lee Dong-Woo
Lam Tuan T.
Myers Bigel & Sibley & Sajovec
Nguyen Hiep
Samsung Electronics Co,. Ltd.
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