Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-06-26
2004-05-18
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S018000, C324S522000, C324S523000
Reexamination Certificate
active
06737671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device testing, and more particularly, to a current measurement circuit and current measurement method for determining the quality of a semiconductor integrated circuit device.
2. Description of the Related Art
Integrated circuits containing very large numbers of devices such as transistors must be tested for defects before they are shipped to customers. A technique called “IDDQ testing” is commonly used in defect testing of integrated circuits containing CMOS devices. IDDQ testing is performed by stopping all clock signals applied to the device under test (DUT). This places the DUT in a quiescent state in which the current flow through the DUT is characterized by a so-called “IDDQ” quiescent current in contrast to the “IDDD” dynamic current which flows during normal clocked operation of the DUT. Various defects or faults can be detected by measuring IDDQ current flow through the DUT when the DUT is in the quiescent state, and comparing the measured IDDQ value to predefined values representative of IDDQ current values for similar devices which are known to be either defective or defect-free. IDDQ testing can be used to detect faults such as bridging faults, transistor stuck-open faults, or gate oxide leaks, which increase the normally low IDDD.
Typically, IDDQ testing is performed by automated test equipment (ATE) which places the DUT in the quiescent state by applying a test pattern electronic signal to the DUT. A parametric measurement unit (PMU) or high precision ammeter is then used to measure the IDDQ current flowing through the DUT. This is an extremely slow technique, in that only a small number of measurements can be included in a production test.
SUMMARY OF THE INVENTION
Accordingly, it is an objective of the present invention to provide a current measurement circuit and method for determining the quality of a semiconductor device which reduces testing time.
It is another aspect of the present invention to provide an on-chip current measurement circuit and method thereof for determining the quality of a semiconductor device which eliminates the need for expensive, external automated test equipment (ATE).
According to one aspect of the present invention, a method for testing a semiconductor device is provided including the steps of providing an integrated circuit including a voltage regulating circuit, the voltage regulating circuit being activated as needed to maintain a required voltage level of the integrated circuit; applying an external voltage to the integrated circuit; monitoring the voltage regulating circuit to determine a number of times it is activated during a sample period; and comparing the number of activations to a predetermined limit whereby if the number of activations exceeds the predetermined limit the semiconductor device is defective.
According to another aspect of the present invention, a semiconductor device including a circuit for determining the quality of the semiconductor device is provided. The semiconductor device includes a voltage regulating circuit for regulating an external voltage to a required internal voltage, the voltage regulating circuit being activated as needed to maintain the required internal voltage; and a current measurement circuit for determining a number of times the voltage regulating circuit is activated and comparing the number of activations to a predetermined limit to determine if the semiconductor device is defective, wherein the number of activations represents a relative current consumption value of the semiconductor device.
According to a further aspect of the present invention, a circuit for determining the quality of a semiconductor device is provided. The circuit includes a current measurement circuit for determining a number of times a voltage regulating circuit of the semiconductor device is activated and comparing the number of activations to a predetermined limit to determine if the semiconductor device is defective, wherein the number of activations represents a relative current consumption value of the semiconductor device. The current measurement circuit includes an external clock for providing a clock signal; a first counter for counting when the voltage regulating circuit is activated; a second counter for counting clock cycles of a sample period; and a register for storing the number of activations from the first counter. Additionally, the voltage regulating circuit being a voltage pump system or a transistor.
REFERENCES:
patent: 6195772 (2001-02-01), Mielke et al.
patent: 363133559 (1986-11-01), None
Moore Philip
Vollrath Joerg
Zimmermann Ulrich
Infineon Technologies Richmond LP
Wille Douglas
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