Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Reexamination Certificate
2000-11-29
2002-11-19
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
C361S093200, C361S018000, C327S540000, C323S274000
Reexamination Certificate
active
06483684
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a current limiting apparatus, and in detail, to a current limiting apparatus for used in a single body power source apparatus and an integrated circuit measuring apparatus.
Referring to
FIG. 5
to
FIG. 8
, the conventional current limiting apparatus will be described.
FIG. 5
is a view showing the circuit structure of a conventional current limiting apparatus
200
. In
FIG. 5
, the conventional current limiting apparatus is structured by a CPU
1
, D/A converters
2
A, and
2
B, resistors
3
A,
3
B, and
3
D, operational amplifiers
4
A and
4
B, transistor
5
, and capacitor
10
. In this conventional current limiting apparatus
200
, its one end is connected to a load
11
structured by a DUT (Device Under Test).
Initially, the structure of this conventional current limiting circuit
200
will be described below. The CPU
1
is connected to the D/A converter
2
A and D/A converter
2
B, and an output terminal of the D/A converter
2
A is connected to a reversal input terminal of the operational amplifier
4
A through the resistor
3
A. Further, non-reversal input terminal of the operational amplifier
4
A is electrically grounded. The output terminal of the operational amplifier
4
A is connected to one end of the capacitor
10
and the load
11
. Further, the other end of the capacitor
10
is electrically grounded. One end of the capacitor
10
and the load
11
are connected to the reversal input terminal of the operational amplifier
4
A through a feedback resistor
3
B. Thereby, a negative feedback closed loop is formed between the output terminal and the reversal input terminal of the operational amplifier
4
A.
Further, the operational amplifier
4
A has a current limiting adjustment terminal A, and the current limiting adjustment terminal A is connected to the collector terminal of the transistor
5
. The output terminal of the operational amplifier
4
B is connected to the base terminal of the transistor
5
, and the output terminal of the D/A converter
2
B is connected to the non-reversal input terminal of the operational amplifier
4
B. The emitter terminal of the transistor
5
is connected to a negative source terminal B through the resistor
3
D. Further, the emitter terminal of the transistor
5
is connected to the reversal input terminal of the operational amplifier
4
B. Thereby, the negative feedback closed loop is formed between the output terminal of the operational amplifier
4
B and the reversal input terminal of the operational amplifier
4
B through the emitter terminal of the transistor
5
.
Next, the operation of the conventional current limiting apparatus
200
in
FIG. 5
will be described. The function of this conventional current limiting apparatus
200
can be divided into 2 kinds of functions, that is, the current limiting function to limit the output current IO of the operational amplifier
4
A by the CPU
1
, and the function in which the input voltage VIN is set by the CPU
1
, and the current IO required by the load
11
is supplied from the operational amplifier
4
A.
Initially, the function to limit the output current IO will be described. The CPU
1
sets the voltage to limit the output current IO of the operational amplifier
4
A by the digital signal, and outputs to the D/A converter
2
B. The D/A converter
2
B converts the inputted digital signal into analog signal, and outputs to the non-reversal input terminal of the operational amplifier
4
B. When this analog signal is inputted, the operational amplifier
4
B generates the potential difference between the base and emitter of the transistor
5
, and the current flows from the base to the emitter. Thereby, the transistor
5
is operated, and the limiting current IA flowing through the current limiting adjustment terminal A of the operational amplifier
4
A is determined according to the relationship of the negative source terminal B, emitter voltage, and resistor
3
D.
When the resistance value of the resistor
3
D is RD, and the voltage value of the negative source terminal B is VB, then, the emitter voltage of the transistor
5
is set by the digital signal outputted from the CPU
1
, and is equal to the voltage value VC converted into the analog value by the D/A converter
2
B, therefore, the limiting current IA flowing in the current limiting adjustment terminal A is
IA
=(
VC−VB
)/
RD
(1).
As described above, by limiting the current flowing in the current limiting adjustment terminal A of the operational amplifier
4
A, the output current IO of the operational amplifier
4
A is limited so that the input current into the load
11
is not excessive. Further, the following relationship exists between the output current IO of the operational amplifier
4
A and the limiting current IA flowing in the current limiting adjustment terminal A:
IO=IA·G
(2).
Herein, G is a current amplification factor of the operational amplifier
4
A. By using the above expressions (1) and (2), the following relational expression is obtained between the current limit voltage VC set by the CPU
1
and the output current IO:
IO=G
·(
VC−VB
)/
RD
(3).
In this expression (3), as shown in
FIG. 6
, the output current IO has a proportional relationship to the current limit voltage VC set by the CPU
1
.
Next, the function to supply the current to the load
11
in the setting of the input voltage will be described. In the conventional current limiting apparatus
200
, the CPU
1
sets the digital signal corresponding to the input setting voltage and outputs to the D/A converter
2
A, and the D/A converter
2
A converts the inputted digital signal into the analog signal and outputs to the resistor
3
A. This analog signal is inputted into the reversal input terminal of the operational amplifier
4
A through the resistor
3
A, and this operational amplifier
4
A amplifies the output voltage to the input setting voltage corresponding to this inputted analog signal. The voltage amplified by the operational amplifier
4
A is outputted to the load
11
, and the operational amplifier
4
A outputs the current IO to be supplied to the load
11
. In this case, the capacitor
10
is charged when the output current flows.
Herein, when the value of the voltage inputted into the reversal input terminal of the operational amplifier
4
A by the digital signal outputted by the CPU
1
, is VIN, the resistance value of the resistor
3
A is R
1
, and the resistance value of the feedback resistor
3
B is R
2
, then, the value VO of the voltage supplied to the load
11
is as follows:
VO
=−(
R
2
/
R
1
)·
VIN
(4).
By this expression (4), the output voltage VO is determined by the input setting voltage VIN. When the capacity of the capacitor
10
is C, the value of the output current is IO, and the value of the output voltage is VO, then, the time t necessary for charging the capacitor is,
t
=(
C·VO
)/
IO
(5),
and when the expression (4) is substituted into the expression (5), it can be clear that the time t necessary for charging the capacitor is, as shown by the following expression, formed of the relationship of the input voltage VIN and output current IO:
t=−C
·(
R
2
/
R
1
)·(
VIN/IO
) (6)
As described above, when the input voltage VIN is set by the CPU
1
, because C, R
1
, and R
2
are respectively known capacity of the capacitor
10
, resistance values of the resistors
3
A and
3
B, the time t necessary for charging the capacitor
10
depends on only the output current IO.
FIG. 7
is a view showing the relationship of t −IO in the expression (6). As can be clearly seen from
FIG. 7
, the output current IO and the time t are in inversely proportional relationship to each other. In the case where the charging current for charging the capacitor
10
is IC, when the output current IO is smaller than the charging current IC, because a long period of time is necessary for charging the capacitor
10
, the time t for supplying
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Huynh Kim
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