Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1997-05-19
1999-10-19
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 58, 326 68, 326 86, H03K 190185
Patent
active
059695412
ABSTRACT:
A tri-state I/O buffer and a method of inhibiting current to an I/O buffer arranged to be powered by a supply voltage and to drive an output terminal are provided. The I/O buffer preferably has an output driving circuit connected to the supply voltage for driving the output terminal and includes a first plurality of transistors defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage and a second plurality of transistors defining a pull-down circuit for operatively connecting the output terminal to ground. An input control circuit is connected to the output driving circuit and the supply voltage, and is arranged to receive a buffer input signal for controlling the buffer input signal to the output driving circuit. A bias controlling circuit is connected to the isolated floating well circuit and the supply voltage, and is arranged to receive a tri-state enabling signal and the buffer input signal for controlling a biasing signal to the floating well circuit.
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Galanthay Theodore E.
Jorgenson Lisa K.
Le Don Phu
Regan Christopher F.
Santamauro Jon
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