Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-03-31
2001-03-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S171000, C365S173000, C365S148000, C365S207000
Reexamination Certificate
active
06205073
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to MTJ memories and more particularly, to apparatus and a method for reading data stored in MTJ memories.
BACKGROUND OF THE INVENTION
Thin film Magnetic Random Access Memories (MRAMs) can be fabricated in a variety of memory cell embodiments, including a Magnetic Tunneling Junction (MTJ) cell. The MTJ cell essentially consists of a pair of magnetic layers with an insulating layer sandwiched therebetween. One of the magnetic layers has a fixed magnetic vector and the other magnetic layer has a changeable magnetic vector that is either aligned with or opposed to the fixed magnetic vector. When the magnetic vectors are aligned the resistance of the MTJ cell, i.e. the resistance to current flow between the magnetic layers, is a minimum and when the magnetic vectors are opposed or misaligned the resistance of the MTJ cell is a maximum.
Data is stored in the MTJ cell by applying a magnetic field to the MTJ cell directed so as to move the changeable magnetic vector to a selected orientation. Generally, the aligned orientation can be designated a logic 1 or 0 and the misaligned orientation is the opposite, i.e., a logic 0 or 1. Stored data is read or sensed by passing a current through the MTJ cell from one magnetic layer to the other. The amount of current passing through the MTJ cell, or the voltage drop across the MTJ cell, will vary according to the orientation of the changeable magnetic vector. Additional information as to the fabrication and operation of MTJ memory cells can be found in U.S. Pat. No. 5,702,831, entitled “Multi-Layer Magnetic Tunneling Junction Memory Cells”, issued Mar. 31, 1998, and incorporated herein by reference.
In the prior art, reading data stored in MTJ cells is achieved by passing a current through a series circuit including a load resistor and the MTJ cell. The current passing through the MTJ cell is controlled by a transistor with a bias voltage on the gate, and an output voltage is obtained at a junction between the load resistor and the current controlling transistor. Also, a bitline and a data line for the MTJ cell (and other MTJ cells in the array) are clamped at a desired voltage by the transistor. There are several major problems with this type of data readout including the fact that the load resistor must be much larger than the resistance of the MTJ cell, which makes operation at low supply voltages very difficult. Also, the operation of the circuit is dependent upon the clamping voltage provided by the transistor and the bias voltage. However, the clamping voltage is a function of the resistance of the MTJ cell, the bias voltage, and the load resistance, any or all of which can vary with a specific readout process, variations in the supply voltage, changes in temperature, changes in the resistance of the MTJ cell, etc. Also, the large load resistance and the other components in this prior art circuit require large chip areas preventing the fabrication of high density memory arrays. Also, the input impedance is high due to the presence of the load resistor.
Accordingly it is highly desirable to provide apparatus and a method of reading or sensing MTJ memory cells which overcomes these problems.
REFERENCES:
patent: 5761110 (2000-08-01), Irrinki et al.
patent: 5774404 (1998-06-01), Eto
patent: 6097625 (2000-08-01), Scheuerlein
Koch William E.
Motorola Inc.
Nelms David
Yoha Connie C.
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