Current controlled open-drain output driver

Details Current controlled open-drain output driver Current controlled open-drain output driver

2000-07-17

2001-09-25

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189050

Reexamination Certificate

active

06295233

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuitry, and in particular to an improved current-controlled open-drain output driver.
Since the adoption of the reduced instruction set computer (RISC) architecture, the central processing unit (CPU) speed has been increasing rapidly year after year. On the other hand, the speed of memory devices such as dynamic random access memory (DRAM) has not nearly kept up with the rapid increase in CPU speed. In fact, the gap between the respective speeds of CPUs and memory devices has been widening in recent years.
Since memory is a common component in digital devices, the speed of the memory in many applications affects the overall performance of digital devices. As a practical matter, a CPU in most cases cannot effectively perform its functions until and unless it receives the requisite data from the appropriate memory device. Hence, the speed difference between CPUs and memory devices has created a performance bottleneck.
In an effort to catch up with the rapid enhancement of CPU performance, a number of improved memory devices, such as Rambus DRAM (RDRAM) and Synchronous DRAM (SDRAM), have been introduced. These improved memory devices generally provide high bandwidth memory transfers by using high speed output drivers. Further information regarding high bandwidth DRAMs can be found in A. Hatakeyama et al., “256 Mb SDRAM Using a Register-Controlled Digital DLL,” ISSCC Digest of Technical Papers, pp. 72-73, February 1997; C. Kim et al., “A 640 MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40 mW DLL Circuit for a 256 MB Memory System,” ISSCC Digest of Technical Papers, pp. 158-159, February 1998; and N. Kushiyama et al., “A 500-Megabytes/s Data-Rate 4.5M DRAM,” IEEE J. Solid-State Circuits, vol. SC-28, pp. 490-498, April 1993.
FIG. 1
illustrates an example of a high speed output driver circuit in accordance with an RDRAM design. An NMOS transistor (NM) has an open-drain design. The drain node of the transistor (NM) is connected in series with an off-chip termination resistor
10
and a termination voltage source
12
through an off-chip transmission line. Typically, the termination resistor
10
has a value of R
T
=40 &OHgr; and the termination voltage source
12
may have a value of V
TT
=1.8V. The drain node voltage of the transistor (NM) is used to provide the output voltage used to drive external devices coupled to the pad (PAD). Hence, the drain node voltage, or conversely, the voltage swing across the termination resistor
10
, should ideally be kept at a stable level. The voltage swing across the termination resistor
10
is determined by the drain (or output load) current I
OL
of the turned-on open-drain NMOS transistor (NM). The drain current in turn is affected by the supply voltage, which in this case is the termination voltage source
12
, and variations in temperature.
Circuit techniques have been developed to keep the output current I
OL
stable and insensitive to variations in temperature and supply voltage. An example can be found in N. Kushiyama et al., “A 500-Megabytes/s Data-Rate 4.5M DRAM,” IEEE J. Solid-State Circuits, vol. SC-28, pp. 490-498, April 1993, and Thaddeus J. Gabara et al., “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers,” IEEE J. Solid-State Circuits, vol. SC-32, pp. 407-418, March 1997. In Kushiyama et al., the open drain NMOS transistor is split into binary-weighted transistors, the ON/OFF condition of which is determined by a digital code. This digital code is generated by an external source in the system and sent to the output driver periodically. The generation of the digital code by an external source necessarily causes overhead in the system. Accordingly, a technique would be desirable for reducing the overhead of generating a digital code from an external source for compensation of temperature and supply voltage variations.
SUMMARY OF THE INVENTION
New methods and circuits for implementing current controlled open-drain output drivers are introduced. The present invention can be incorporated into a number of digital devices which utilize output drivers including, for example, high bandwidth memory circuits.
In an exemplary embodiment, the present invention includes an on-chip current control circuit, a switching controller, and a first group of binary-weighted switching devices arranged in a parallel configuration, all of which are implemented on an integrated circuit chip. The current control circuit continually generates a digital code which is passed onto the switching controller. Using the digital code, the switching controller activates or deactivates the appropriate binary-weighted switching devices accordingly thereby maintaining a relatively stable output current I
OL
for the output driver.
In another embodiment, the present invention further includes a current control recording device, preferably, implemented in the form of a register. The current control recording device periodically records the digital code generated by the current control circuit and then passes the digital code onto the switching controller.
In a further embodiment, the current control circuit in accordance with the present invention includes a comparator, an up/down counter, a bandgap reference current generator, and a second group of binary-weighted switching devices arranged in a parallel configuration. The bandgap reference current generator provides a relatively stable current source for the second group of binary-weighted switching devices. The comparator generates a comparison result based on a comparison of the drain node voltage of the second group of binary-weighted switching devices with a reference voltage. The comparison result is used by the up/down counter to generate the digital code. The digital code, in turn, is fed back to the second group of binary-weighted switching devices to effect their appropriate activation or deactivation. The digital code is also fed to the switching controller thereby causing the first group of binary-weighted switching devices to be turned on/off appropriately. By configuring the current control circuit in the foregoing manner, a feedback loop is formed to generate a digital code which can then be used to maintain a relatively stable voltage at the output of the output driver.
The present invention provides a number of advantages over conventional output drivers. For example, by implementing the output driver on an integrated circuit chip in accordance with the present invention, the overhead of generating a digital code from an external source to maintain a stable voltage at the output of the output driver is reduced. Furthermore, by using a bandgap reference current generator as part of the output driver, the output current of the output driver can be maintained at a relatively stable level with regard to any variation in temperature and/or supply voltage.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings, like reference numbers indicate identical or functionally similar elements.


REFERENCES:
patent: 5255222 (1993-10-01), Eaton, Jr.
patent: 5903501 (1999-05-01), Vurosaki
patent: 5917758 (1999-06-01), Veeth
patent: 5959926 (1999-09-01), Jones
Kim et al., “A 640MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40mW DLL Circuit for a 256MB Memory System,”ISSCC Digest of Technical Papers, pp. 158-159 (Feb. 1998).
Gabara et al., “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers,”IEEE J. Solid-State Circuits, vol. SC-32, pp. 407-418 (Mar. 1997).
Hatakeyama et al., “A 256Mb SDRAM Using a Register-Controlled Digital DLL,”ISSCC Digest of Technical Papers, pp. 72-73 (Feb. 1997).
Kushiyama et al., “

Affiliated with

Also associated with

Rating

Current controlled open-drain output driver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current controlled open-drain output driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current controlled open-drain output driver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2454496