Current control circuit for dynamic memory

Details Current control circuit for dynamic memory Current control circuit for dynamic memory

1991-05-17

1993-07-20

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365227, 36523008, G11C 700, G11C 1140

Patent

active

052299660

ABSTRACT:
As latch circuit is supplied with a readout control signal for reading out data and a reference voltage for determining "1" or "0" of address data. The latch circuit latches address data for selecting a memory cell array according to the readout control signal and the reference voltage. A reference voltage generation circuit for generating the reference voltage includes resistors connected between first and second power sources and an output node which is connected between the resistors and from which the reference voltage is output. A transistor serving as an interruption circuit for interrupting the current path is connected between the first power source and the resistor. The transistor is turned off to interrupt a through current flowing between the first and second power sources when the readout signal is set in the stand-by state.

REFERENCES:
patent: 4937789 (1990-06-01), Matsubara
patent: 5001668 (1991-03-01), Ito et al.

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