Cu seed layer deposition for ULSI metalization

Details Cu seed layer deposition for ULSI metalization Cu seed layer deposition for ULSI metalization

2001-02-20

2003-01-28

Powell, William A. (Department: 1765)

Etching a substrate: processes

Nongaseous phase etching of substrate

Irradiating, ion implanting, alloying, diffusing, or...

C216S088000, C216S099000, C216S100000, C438S692000, C438S745000, C438S754000, C438S756000

Reexamination Certificate

active

06511609

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method for Cu seed layer deposition for ultra large scale intergration ULSI metalization, especially to a method for forming a Cu seed layer by replacing a poly silicon, amorphous silicon or TaSix layer in ULSI metalization.
BACKGROUND OF INVENTION
In the ULSI process, in order to reduce the RC delay time, it is necessary to form a Cu layer to replace Al. Due to the relatively low cost, the electric plating process of Cu layer is well accepted in the industry. In such a process, before a Cu layer is platted to the wafer, a seed layer is applied to the surface of the wafer to get good electrode surface, such that high quality of plating may be obtained. The seed layer is a thin Cu layer on the surface on which a metal layer will be platted. The seed layer may be deposited to the surface of the silicon dioxide or wafer. However, when vias with greater aspect ratio exist on the surface of the wafer, poor conformality in the physical vapor deposition (PVD) deposition of the seed layer will happen. As a result, the chemical vapor deposition (CVD) is used to solve such a problem.
Christine Whitman et al. suggested that the cluster MOCVD-Cu process is capable of depositing conformal and low-resistive copper seed layers with satisfactory adhesion for subsequent copper filing by either electrochemical deposition or MOCVD. (See Christine Whitman, Mehrdad M. Moslehi, Ajit Paranjpe, Lino Velo, and Tom Omstead, J. Vac. Sci. Technol. A 17(4), 1893, 1999) Although the CVD process is able to produce a qualified Cu seed layer, its high cost makes it impossible to reduce the manufacture cost of the ULSI preparation.
Robert Mikkola et al. disclosed a method for forming a Cu seed layer by PVD depositing a 1,000 Å Cu seed layer onto a 200 Å Ta adhesion layer. According to their experiments, when the thickness of the Cu layer is 1,000 Å at the side wall of the vias, it is possible to fill up vias with a diameter of 0.25 &mgr;m and an aspect ratio of 4. Resistivity of the as-deposit layer so prepared is 0.25 &mgr;&OHgr;-cm. After self-annealing for 40 hours under the room temperature or 20 minutes under 80° C., its resistivity may be reduced to 1.85 &mgr;&OHgr;-cm. (See R. D. Mikkola et al., “Copper electroplating for advanced interconnect technology”, Plating and Surface Finishing, March 2000, P.81.) However, using this approach, the step coverage of the PVD film will be a problem for filling up vias with high aspect ratio.
Yuri Lantasov et al. disclosed a method of electroless electroplating copper to replace an activated Pd adhesion layer to form the seed layer. According to Lantasov et al., this approach is able to fill up vias on the wafer with a via diameter of 0.35 &mgr;m and an via aspect of 3. This approach, however, is not suited to wafers with vias of higher aspect ratio, since the Pd layer is sputtered on the surface of the wafers. (See Yuri Lantasov et al., “New plating bath for electroless copper deposition on sputtered barrier layers”, Microelectronic Engineering, 50, 2000, p. 441.)
M. J. Shaw disclosed a method of directly depositing a copper film onto a silicon substrate with the photo-CVD technology under ambient pressure and under 240° C., by using Cu(hfac)
2
as reactant. (See M. C. Shiao, “Study on selective deposition of Cu films on Si (100) substrates at ambient pressure”, National Chiao Tung University, MSECG, 1998, pt 1:2.) Under this approach, however, the resistivity of the copper film so prepared was 8.88 m&OHgr;-cm.
M. K. Lee et al. disclosed a method of chemical replacing silicon with copper directly to form a copper film under room temperature. When the thickness of the copper film is 5,000 Å, a low resistivity of 2.16 &mgr;&OHgr;-cm may be obtained. (See M. K. Lee et al., “Deposition of copper films on silicon for cupric sulfate and hydrofluoric acid”, Journal of Electrochemical Society, Vol. 144, No. 5, May 1997.) In this paper, Lee et al. did not consider the existence of the diffusion barrier and the adhesion layer for Cu interconnection. As a result, a processing to suppress the diffusion of copper is needed.
It is thus necessary to provide a novel method of Cu seed layer deposition for ULSI metalization.
It is also necessary to provide a low-cost and simplified method of Cu seed layer deposition for ULSI metalization.
It is also necessary to provide a method of Cu seed layer deposition for ULSI metalization that is suited in substrates with vias of greater aspect ratio.
It is also necessary to provide a method of Cu seed layer deposition for ULSI metalization wherein problems brought by byproducts of reaction may be avoided.
OBJECTIVES OF INVENTION
The objective of this invention is to provide a novel method of Cu seed layer deposition for ULSI metalization.
Another object of this invention is to provide a low-cost and simplified method of Cu seed layer deposition for ULSI metalization.
Another object of this invention is to provide a method of Cu seed layer deposition for ULSI metalization that is suited in substrates with vias of greater aspect ratio.
Another object of this invention is to provide a method of Cu seed layer deposition for ULSI metalization wherein problems brought by byproducts of reaction may be avoided.
SUMMARY OF INVENTION
According to this invention, a novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing the poly silicon layer, amorphous silicon layer or TaSix layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer, amorphous silicon layer or TaSix layer with copper and to reduce the quantity of byproducts of the reaction.
These and other objectives and advantages of this invention may be clearly understood from the detailed description by referring to the following drawings.


REFERENCES:
patent: 6211090 (2001-04-01), Durlam et al.
patent: 6225226 (2001-05-01), Lee et al.
Ultralarge Scale Integrated Metallization and Interconnects, Christine Whitman, J. Vac. Sci. Technol. A 17(4), Jul./Aug. 1999; pp. 1893-1897.
Copper Electroplating For Advanced Interconnect Technology, Mikkola et al., Plate and Surface Finishing, Mar. 2000, pp. 81-85.
New Plating Bath for Electroless Copper Deposition on Sputtered Barrier Layers; Lantasov et al., Microelectronic Engineering 50 (2000), pp. 441-447.
Study on Selective Deposition of Cu Films on Si(100) Substrates at Ambient Pressure; Dr. Cheng-Tzu Kuo, Institute of Materials Science and Engineering National Chiao Tung University; pp. ii-iii.
Deposition of Copper Films on Silicon from Cupric Sulfate and Hydrofluoric Acid; Lee et al., J. Electrochem. Soc., vol. 144, No. 5, May 1997, pp. 1777-1780.

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