Cryptographic accelerator

Electrical computers and digital processing systems: support – Data processing protection using cryptography

Reexamination Certificate

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Details

C380S030000, C380S044000, C380S044000, C380S028000, C380S044000, C380S037000, C713S193000, C713S153000, C713S194000

Reexamination Certificate

active

06963979

ABSTRACT:
A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) manages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.

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