Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-30
2001-04-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000
Reexamination Certificate
active
06222219
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to a process for fabricating a crown capacitor using steps which include tapered etching and chemical mechanical polishing to form a bottom electrode and a crown-like structure in the capacitor. No side wall spacers, as required in prior art processes, are utilized in the process of the present invention.
In accordance with the present invention, a tapered etch is used to form a trough in a planarized interlevel dielectric material, e.g. doped SiO
2
, of a semiconductor structure and is performed over a contact hole forming a “crown-like structure.” The contact hole and, optionally, the crown are then covered by a conductor material, which is patterned by chemical mechanical polishing to form the bottom electrode of the capacitor. The process of the present invention is simple, requiring no additional processing steps or side wall spacers as required by prior art processes, and it provides a nearly planar surface after formation of the plate electrode.
A crown capacitor structure containing a damascene bottom electrode is also provided by the present invention. It is emphasized that the crown capacitor structure of the present invention has an increased electrode area compared to conventional stacked capacitors. Moreover, the crown capacitors of the present invention have a nearly planar topography which eliminates the need for extra processing steps that are typically required in the prior art to fabricate crown capacitors having a planarized surface.
2. Prior Art
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) cell comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a field effect transistor for opening and closing charge and discharge passages of the capacitor. The number of bits on DRAM chips has been increasing by approximately 4× every three years; this has been achieved by reducing the cell size. Unfortunately, the smaller cell size also results in less area to fabricate the capacitor.
In early DRAM generations, the storage electrode of each capacitor which constitutes each memory cell, together with each corresponding field effect transistor, was formed in the shape of a planar plate over the field effect transistor. Because of this planar plate shape, the storage electrode surface area was abruptly reduced as the cell size decreased. In this regard, conventional methods for fabricating memory cells have difficulties in increasing the surface area of storage electrodes because they involve the formation of a storage electrode having a planar plate shape.
In order to increase the electrode area and hence capacitance of DRAM cells, stacked capacitors, such as 5 described in Japanese Patent No. 07-45718 and Japanese Patent No. 06-224385, and crown capacitors, such as described in T. Kaga, et al., IEEE Trans. Elec. Dev., Vol. 38, 1991, p. 255 and U.S. Pat. No. 5,552,234 to Tseng, have been employed.
Conventional stack capacitors provide increased electrode area using simple processing steps including deposition and etching of a bottom electrode. A conventional stacked capacitor prepared from prior art processes is shown in FIG.
1
. Specifically,
FIG. 1
shows a semiconductor substrate
1
, a dielectric material
2
formed on the surface of semiconductor substrate
1
, a bottom electrode
3
, a node dielectric material
4
and a plate electrode
5
. The dielectric material
2
contains wordline
6
, bitline
8
and bitline contact
7
. Due to the additional area provided by the sidewalls of the bottom electrode, this conventional stacked capacitor has an increased surface area compared to planar capacitors.
However, for a given dielectric material, the only way to increase the area of the conventional stack capacitor is to make the bottom electrode taller, which introduces severe topography between the array and the support circuits. This severe topography reduces the process window for lithography and may require an additional chemical mechanical polishing step to replanarize the surface. Moreover, as the neight of stack capacitor increases, the planarization step becomes increasingly expensive.
For a given stacked capacitor height, crown capacitors can provide more electrode area (80% or more) than simple stacked capacitors. Despite this increase in electrode area, prior art crown capacitors require additional processing steps which subsequently add to the cost of their manufacturing. For instance, in a process which forms a single crown, as disclosed in the Kaga, et al. reference mentioned above, at least five additional processing steps are required. These additional processing steps include: mandrel oxide deposition and etch, plug oxide deposition and etch, and mandrel oxide/plug oxide removal. In addition, topography (though less than that of conventional stacked capacitors) is still created by the crowns, which may add extra planarization steps in their fabrication.
In view of the drawbacks mentioned hereinabove concerning conventional stacked capacitors and conventional crown capacitors, there is a need to develop new processes which provide increased electrode area and a nearly planar topography to a capacitor without requiring a lot of extra processing steps.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process for fabricating a crown capacitor containing a damascene bottom electrode which has an increased area as compared to conventional stack capacitors without using side wall spacers.
Another object of the present invention is to provide a process for fabricating a crown capacitor which has nearly the equivalent electrode area as standard crown capacitors, but does not require the use of extra processing steps, as compared to conventional processes for fabricating crown capacitors.
A further object of the present invention is to provide a process that directly results in a planarized topography so as to eliminate the need for using additional processing steps which are typically required in prior art processes of fabricating crown capacitors or stacked capacitors.
These as well as other objects are achieved by the present invention which utilizes steps including a tapered etch and chemical mechanical polishing to form the bottom electrode and the crown.
Specifically, in one embodiment of the present invention, a process for fabricating a crown capacitor containing a damascene bottom electrode is provided which comprises the steps of:
(a) providing a semiconductor structure comprising a semiconductor substrate having appropriate diffusion and isolation regions, at least one wordline, at least one bitline, at least one bitline contact for connecting said bitline to said semiconductor substrate, and a planarized interlevel dielectric material, wherein said interlevel dielectric material is on top of said planarized semiconductor substrate and surrounds said bitline, bitline contact and wordline;
(b) forming a contact hole in said planarized interlevel dielectric material between said wordlines to expose an area of said semiconductor substrate;
(c) forming a trough in said planarized interlevel dielectric material at said contact hole, wherein said trough does not extend all the way through said contact hole;
(d) depositing a bottom electrode material into said contact hole and said trough, wherein said bottom electrode material comprises a conductor;
(e) patterning the bottom electrode material provided in step (d) by chemical mechanical polishing;
(f) depositing a node dielectric material on said patterned bottom electrode material and on said planarized interlevel dielectric material;
(g) optionally, subjecting the structure provided in step (f) to thermal oxidation under conditions effective to diffuse oxygen into said node dielectric material; and
(h) depositing a plate electrode on said node dielectric material or said thermally oxidized node dielectric material.
It is emphasized that in step (c) of the
Gambino Jeffrey P.
Kotecki David E.
Anderson, Esq. Jay H.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Thomas Tom
Tran Thein F
LandOfFree
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