Crow-bar current reduction circuit

Details Crow-bar current reduction circuit Crow-bar current reduction circuit

1998-03-06

2000-10-17

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 27, 326 58, H03K 19003, H03K 1902

Patent

active

06133748&

ABSTRACT:
A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.

REFERENCES:
patent: 5165046 (1992-11-01), Hesson
patent: 5210449 (1993-05-01), Nishino et al.
patent: 5239214 (1993-08-01), Segawa et al.
patent: 5568081 (1996-10-01), Lui et al.
patent: 5594380 (1997-01-01), Nam

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