Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-19
2006-09-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07111259
ABSTRACT:
A method and system of crosstalk mitigation in integrated circuits employs delay change curves (DCCs) and uses targeted transistor sizing and/or buffer insertion. Based on a timing graph, a longest path capable of being shortened may be shortened by victim strengthening or aggressor weakening when a setup requirement time violation occurs and the path is capable of being shortened. The process is repeated based on an updated timing graph until the longest path is not capable of being further shortened, or there is no setup requirement time violation. Additionally, the path may be lengthened where a hold requirement time violation has occurred and the path is capable of being lengthened, by victim strengthening or aggressor weakening, until the path cannot be further lengthened or there is no hold requirement time violation. Victim strengthening is performed by altering the critical path, and aggressor weakening is performed by altering the non-critical path.
REFERENCES:
patent: 5568395 (1996-10-01), Huang
patent: 5983006 (1999-11-01), Carlson et al.
patent: 6058256 (2000-05-01), Mellen et al.
patent: 6128769 (2000-10-01), Carlson et al.
patent: 6263478 (2001-07-01), Hahn et al.
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6389581 (2002-05-01), Muddu et al.
patent: 6434731 (2002-08-01), Brennan et al.
patent: 6449753 (2002-09-01), Aingaran et al.
patent: 6499131 (2002-12-01), Savithri et al.
patent: 6507935 (2003-01-01), Aingaran et al.
patent: 6532574 (2003-03-01), Durham et al.
patent: 6587815 (2003-07-01), Aingaran et al.
patent: 6594805 (2003-07-01), Tetelbaum et al.
R. Arunachalam, K. Rajagopal and L. T. Pileggi, “TACO: Timing Analysis With Coupling,” ACM/IEEE Design Automation Conference, (DAC2000), pp. 266-269.
Y. Cao, T. Sato, X. Huang, C. Hu, and D. Sylvester, “New Approaches to Noise-Aware Static Timing Analysis,” ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU2000), pp. 8-13.
A. Devgan, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” IEEE/ACM International Conference on Computer-Aided Design, (ICCAD97), pp. 147-151.
T. Xiao and M. Marek-Sadowska, “Worst Delay Estimation in Crosstalk Aware Static Timing Analysis,” Proceedings of International Conference on Computer Design, (ICCD2000), pp. 115-120.
T. Xiao, C.-W. Chang, M. Marek-Sadowska, “Efficient Static Timing Analysis in Presence of Crosstalk,” 13thAnnual International ASIC/SOC Conference, 2000, pp. 335-339.
P.F. Tehrani, S.W. Chyou, U. Ekambaram, “Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk,” IEEE 1stInternational Symposium on Quality Electronic Design, (ISQED2000), pp. 505-512.
S. Sapatnekar, “Capturing the Effect of Crosstalk on Delay,” 13thInternational Conference on VLSI Design, Jan. 2000, pp. 364-369.
T. Sato, D. Sylvester, Y. Cao, and C. Hu, Accurate In-situ Measurement of Peak Noise and Signal Delay Induced by Interconnect Coupling, IEEE International Solid-State Circuits Conference, (ISSCC2000), pp. 226-227.
Y. Sasaki and K. Yano, “Multi-Aggressor Relative Window Method for Timing Analysis Including Crosstalk Delay Degradation,” IEEE Custom Integrated Circuits Conference, (CICC2000), pp. 495-498.
Y. Sasaki and G. De Micheli, “Crosstalk Delay Analysis using Relative Window Method,” 12thAnnual International ASIC/SOC Conference, 1999, pp. 9-13.
P. Rezvani, A.H. Ajami, M. Pedram, and H. Savoj, “LEOPARD: A Logical Effort-based fanout Optimizer for Area and Delay,” IEEE/ACM International Conference on Computer-Aided Design, (ICCAD99), pp. 516-519.
P.D. Gross, R. Arunachalam, K. Rajogopal, and L.T. Pileggi, “Determation of Worst-Case Aggressor Alignment for Delay Calculation,” IEEE/ACM International Conference on Computer-Aided Design, (ICCAD98), pp. 212-219.
L.P.P.P. van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” IEEE International Symposium on Circuits and Systems, (ISCS90), pp. 865-868.
T. Xiao and M. Marek-Sadowska, “Efficient Delay Calculation in Presence of Crosstalk,” Proceedings of 1stInternational Symposium on Quality Electronic Design, (ISQED2000), pp. 491-497.
B. Franzini, C. Forzan, D. Pandini, P. Scandolara, A. Dal Fabbro, “Crosstalk Aware Static Timing Analysis: a Two Step Approach,” IEEE 1stInternational Symposium on Quality Electronic Design, (ISQED2000), pp. 499-503.
Y. Eo, W.R. Eistenstadt, J.Y. Jeong and O.-K. Kwon, “A New On-Chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design,” IEEE Transactions on Electron Devices, vol. 47, No. 1, Jan. 2000.
A. Devgan, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” IEEE/ACM International Conference on Computer-Aided Design, (ICCAD97), pp. 147-151.
J. Cong, D.Z. Pan and P.V. Srinivas, “Improved Crosstalk Modeling of Noise Constrained Interconnect Optimization,” ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, (TAU2000), pp. 14-20.
S. Sirichotiyakul, D. Blaauw, R. Levy, C. Oh, S. Shams, V. Zolotov and J. Zuo, “Driver Modeling and Alignment for Worst-Case Delay Noise.” ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, (TAU2000), pp. 1-7.
Siek Vuthe
Tat Binh
LandOfFree
Crosstalk mitigation method and system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Crosstalk mitigation method and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Crosstalk mitigation method and system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3550484