Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-15
2004-08-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06772403
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an analysis method for crosstalk between many aggressor wires in semiconductor integrated circuit devices and an electronic circuit device having such integrated circuit devices mounted on a printed circuit board or the like, a method for calculating delay times, a method for designing/manufacturing electronic circuit device by using the same, and the like.
BACKGROUND ART
In realizing a logic circuit, there is used up to now a method by which, after arranging large and small electronic circuits known as circuit cells or blocks (also called circuit units), each having a certain logical function, over a semiconductor integrated circuit chip, in a package or over a substrate, the input/output terminals of the cells or blocks are connected using metal wiring.
Since minimizing the area of the semiconductor IC chip, package module or substrate-mounted system to be designed would mean an economic advantage, it is desirable to maximize the integrating density or mounting density of the cells, blocks or wiring. For this reason, in the production of semiconductor integrated circuits, an ever higher degree of fineness has been sought in processing technique and, in respect of mounting techniques, ever greater density has been pursued in mounting within packages or over substrates. However, trying to house many elements or wires in a limited area gives rise to many problems, including one of signal crosstalk.
Signal crosstalk means interference between signals that is apt to arise between a plurality of wires arranged in positions physically close to each other. Generally, integrated circuits and systems are designed to enable the functions to be processed by their circuits to be completed within prescribed lengths of delay time so that they can operate at the target frequency given by the respective specifications.
If they are designed without taking into account the crosstalk mentioned above, the variations in delay time invited by the interference between signals will be overlooked, and this might make it impossible for the semiconductor integrated circuit chips or the systems to operate at their respective target frequencies. To avoid such a consequence, there is needed a method by which delay degradations due to crosstalk can be analyzed precisely.
Such crosstalk analysis methods are disclosed in the Japanese Patent Laid-open No. H7-98727, Japanese Patent Laid-open No. H11-40677 and Japanese Patent Laid-open No. H11-154709.
Although the above-cited methods according to the prior art are effective for crosstalk analysis, they are subject to various constraints in actual application to the designing of a delicate and large-scale electronic circuit device because they are based on limiting conditions, and therefore it is difficult to apply them to the designing of actual, complex electronic circuit devices.
For instance, since there is a constraint on the signal transition time of aggressor wires, it can be mentioned that the signal arrival time of a victim wire and that of an aggressor wire greatly influences the delay time. Another constraint is the dynamic dependence of the arrival time of a signal at each wire on its input pattern, which makes it particularly difficult to calculate accurately and efficiently the delay time due to crosstalk in a high-speed and large-scale electronic circuit device in which a large number of aggressor wires are present.
The present invention is intended to provide a novel crosstalk analysis method for solving these problems, and thereby to make it possible to design and manufacture high-speed and large-scale electronic circuit devices realistically and efficiently.
More specifically, the invention is intended to provide a novel method, for use with high-speed and large-scale electronic circuit devices in which, adjacent to one victim wire, a plurality of other wires are arranged, to calculate accurately and efficiently the crosstalk-deriving complex delay degradation that this plurality of aggressor wires inflict on the victim wire.
DISCLOSURE OF INVENTION
As explained above, what poses difficulty in crosstalk analysis is the dependence of its impact on the signal arrival time.
In view of this point, the present inventors proposed in “Cross-talk Delay Analysis using Relative Window Method,” Proceedings of IEEE International ASIC/SOC Conference 1999, pp. 9-13 (hereinafter abbreviated to RWM or referred to as Reference 1), a new analysis method for overcoming these constraints.
Thus, as shown in
FIG. 1
, the problem is that, depending on the relative timing between the signal arrival time on a wire
3
whose delay time is to be analyzed (hereinafter referred to as victim wire or Victim) (hereinafter referred to as VSAT: victim signal arrival time) and the signal arrival time on a wire
4
interfering with it (hereinafter referred to as aggressor wire or Aggressor) (hereinafter referred to as ASAT: aggressor signal arrival time), the delay time varies in many different ways and thereby invites a delay degradation (hereinafter its magnitude will be referred to as delay degradation value).
Incidentally, here is deliberate taken up a case in which the signals reaching at the respective nodes of wires are in a relationship of out-phase-transition as shown in the left part of FIG.
1
. Although there would be no difference in basic idea even if those signals were in a relationship of in-phase-transition, the delay time would be shorter than in the case of out-phase-transition.
In this Reference
1
, in considering the influence of the signal arrival time, a relative signal arrival time (hereinafter referred to as RSAT: relative signal arrival time) which is obtained by assessing the ASAT with reference to the VSAT, is used. Here is prepared in advance a graph or table of delay degradation values with the relative signal arrival time RSAT represented on the horizontal axis as shown in
FIG. 2
for each combination of drivers for the victim and the aggressor (e.g. NAND gate output drive circuits), and the delay degradation value is calculated for each actual case with reference to this graph or table.
A factor further complicating this problem is that the VSAT and the ASAT themselves dynamically vary, dependent on the input patterns (including paths) of the respective arriving signals.
FIG. 3
illustrates this point. For instance, in one type of input pattern variation, whereas the signal is transmitted from an input node in
1
to a node n
2
via a node n
1
, the signal arrival time at the n
2
point in this case is 0.40 ns. In another type of input pattern variation, however, the signal is transmitted from in
3
to n
2
, and the signal arrival time at the n
2
point in this case is 0.10 ns, different from the value mentioned above. Since the RSAT cannot be uniquely determined for this reason, the degradation graph or table such as the one shown in
FIG. 2
cannot be simply applied.
The technique proposed in Reference addresses this problem by resorting to a concept known as the relative window.
The method is illustrated in FIGS.
4
(
a
),
4
(
b
) and
4
(
c
). Since the VSAT and the ASAT dynamically vary with the input pattern, neither of them can be obtained as one point of time. Therefore, as shown in FIG.
4
(
a
), the VSAT and the ASAT are calculated as windows each having a range (or width) of time in which a signal has a possibility of actually arriving. The windows will be referred to as the VSAT window and the ASAT window, respectively.
Next, as the RSAT cannot be determined uniquely, instead it is calculated as a window having a width (hereinafter referred to as relative window) as shown in FIG.
4
(
b
). The relative window here means the range from a time when the RSAT is at its minimum to a time when the RSAT is at its maximum. It is when the ASAT is at its minimum and the VSAT is at its maximum that the RSAT is at its minimum. Conversely, the RSAT is at its maximum when the ASAT is at its maximum and the VSAT is at its minimum. Thus, Min (RSAT)=Min (ASAT)−Max (VSAT) and Max (RSAT)&e
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Lin Sun James
Siek Vuthe
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