Crossed strapped VSS layout for full CMOS SRAM cell

Details Crossed strapped VSS layout for full CMOS SRAM cell Crossed strapped VSS layout for full CMOS SRAM cell

2002-05-16

2003-05-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S238000

Reexamination Certificate

active

06569723

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to CMOS Static RAM (SRAM) integrated circuit devices.
2. Description of Related Art
U.S. Pat. No. 5,831,315 of Kengeri et al. for “Highly integrated low voltage SRAM array with low resistance Vss lines” shows an SRAM array configuration with SRAM cells arranged in rows and columns. Word lines and Vss connections are strapped by an array of word line straps and an array of Vss straps formed from the same layer. The word lines, the Vss straps, the rows and a shared power supply member are all disposed in a first direction. Cell rows are each driven by a particular word line. Cell row pairs are supplied with a low power supply voltage Vss by several Vss connections parallel to the cell rows. The word line straps and Vss straps are offset with respect to their associated word lines and Vss connections, respectively. The Vss strap offset is made by use of a Vss line that makes contact with the Vss connections and further includes landing portions which extend in the column direction and make contact with the Vss straps.
U.S. Pat. No. 5,589,415 of Blanchard for a “Method for Forming a Semiconductor Structure with Self-aligned Contacts” shows an SRAM layout. Local interconnect structures and processes use dual-doped polysilicon. A single implant dopes part of the polysilicon local interconnect layer p-type, and also diffuses through the polysilicon interconnect layer to enhance the doping of the PMOS drain regions, and also (optionally) adds to the doping of the PMOS source regions to provide source/drain asymmetry. The polysilicon interconnect layer is clad to reduce its conductivity, optionally with patterned rather than global cladding so that the diode can be used as a load element if desired.
U.S. Pat. No. 5,745,404, of Lien et al. for an “ISRAM Layout and Structure” shows an SRAM with an upper polysilicon layer forming a strapping via. A triple-polysilicon process forms an SRAM which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
Integrated circuit (IC) memory devices are made up of a plurality of memory cells. In general, one basic memory cell design is duplicated numerous times to form those cells. The basic cell design may be modified slightly from cell to cell, for example one cell may be a reversed image or complement of an adjacent cell, but the entire memory device can be described according to the basic cell design.
In the case of Static Random Access Memory (SRAM) devices, the basic cell is usually in one of two forms, either a six transistor (6T) cell or four transistor/two resistor (4T/2R) cell. Many conventional SRAMs using a 6T configuration have six transistors formed in a bulk semi-conductor substrate such as single crystal silicon. That type of SRAM is usually embodied in a Complementary Metal Oxide Semiconductor (CMOS) technology, with four transistors being N-channel devices while the remaining two transistors are P-channel devices. A 6T SRAM device operates at relatively low power levels and the bulk transistors have good electrical characteristics, including high mobility and low threshold voltages. Also 6T SRAMs are relatively stable, having high immunity to cell errors, such as those caused by incident alpha particles. However, 6T SRAM cells formed of transistors in a bulk substrate require a large area because the transistors are formed next to one another in the substrate and are essentially in the same plane; which use of six bulk transistors imposes an undesirable lower limit on the cell size. Achieving the smallest cell size with the simplest process reduces the manufacturing costs, increases memory capacity, and increases the device performance without increasing the overall device size.
SUMMARY OF THE INVENTION
The invention teaches a cross Vss strapped layout for a SRAM cell.
An object of this invention is to avoid affecting other cells if one cell is shorted to the power supply voltage Vcc line or the bit line which affects the ground Vss of many other cells in a conventional array.
This method of this invention forms the SRAM device of this invention with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage line (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors. Form a first Vss strap/conductor in a first direction in a first one of the metallization layers. Form a second Vss strap/conductor in a second direction in a second one of the metallization layers. Form a VIA/contact between the conductive reference potential node and the first and second Vss strap/conductors. Preferably, the plurality of metallization layers are sandwiched between a plurality of dielectric layers includes a first (M
1
) metallization layer, a second (M
2
) metallization layer, and a third (M
3
) metallization layer. The M
1
layer provides cell local interconnect to connect to drain regions of pull-up and pull-down transistor. The M
1
layer provides conductors for connecting to power supply voltage line Vcc and to the reference potential line Vss. The M
2
layer includes conductors providing power supply voltage Vcc and Vss low resistance straps oriented in the second direction adapted for global connection to every cell. The M
2
layer provides a word line strapping conductor (M
2
B) oriented in the second direction. The M
3
layer provides a Vss low resistance vertical conduction strap oriented in the first direction adapted for global connection to every cell. The M
3
layer provides bit line conductors oriented in the first direction adapted for connection to every cell.


REFERENCES:
patent: 6376297 (2002-04-01), Porter et al.

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