Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2003-05-21
2004-10-05
Rinehart, Mark H. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S113000, C370S351000
Reexamination Certificate
active
06801978
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a crossbar circuit.
2. Description of the Related Art
One example of a conventional crossbar is disclosed in FIG. 1 of Unexamined Japanese Patent Application KOKAI Publication No. H11-212927. According to the crossbar disclosed in this publication, if the number of inputs increases, the structure of the crossbar become complicated and wiring delay and logical delay become larger, resulting in that the time required for processing is increased.
To solve this problem, the inventor of the present invention has got an idea that registers for retaining a data piece and an arbitration result generated by an arbiter should be provided on a data path and a path through which the arbitration result flows. A block diagram representing a data exchange system employing a crossbar
440
having this structure is shown in FIG.
9
.
As shown in
FIG. 9
, this data exchange system comprises requesters
400
and
410
, and the crossbar
440
.
The requester
400
includes an output data register
401
, an output control circuit
402
, and a request register
403
, and outputs a data piece and a request to the crossbar
440
. The output control circuit
402
receives selection signals from selection registers
423
and
433
of the crossbar
440
. In a case where the received selection signal represents that “a preceding data piece has been allowed to be output to a crossbar output port OP
0
or OP
1
”, the output control circuit
402
sets a following data piece in the output data output control circuit
402
sets a following data piece in the output data register
401
, and sets a request corresponding to the following data in the request register
403
. The output data register
401
outputs the data piece set therein to a relay register
425
, and the request register
403
outputs the request set therein to a request decoder
421
.
The requester
410
has the same structure and functions as those of the requester
400
, and is connected to another input port of the crossbar
440
.
The crossbar
440
comprises crossbar output data registers
450
and
451
, selectors
424
and
434
, arbiters
422
and
432
, selection registers
423
and
433
for retaining arbitration results of the arbiters
422
and
432
respectively, and relay registers
425
and
435
for retaining data pieces.
The request decoders
421
and
431
converts requests (information (request information) for specifying the requester, output destination, priority, etc.) input from the requester
400
and the requester
410
respectively, into request signals, and outputs the request signals to either of the arbiter
422
and the arbiter
423
that corresponds to the crossbar output port designated in the requests. The arbiters
422
and
432
arbitrate the requests input from the requesters
400
and
410
in accordance with the supplied request signals, and output a selection signal representing an arbitration result to the selection register
423
or the selection register
433
. The selection registers
423
and
433
supply the selection signal to the selectors
424
and
434
respectively, and to the requesters
400
and
410
respectively. The relay registers
425
and
435
retain data pieces input by the requesters
400
and
410
to the crossbar
440
. Each of the relay registers
425
and
435
outputs the retained data piece to the selectors
424
and
434
. The selectors
424
and
434
select one of the two data pieces supplied thereto in accordance with the selection signal output from the selection register
423
or
433
, and set the selected data piece in the crossbar output data registers
450
and
451
respectively. The crossbar output data registers
450
and
451
output the set data to the crossbar output ports OP
0
and OP
1
.
An operation clock is supplied to each component described above, so that the components can operate synchronously. For example, the output data registers
401
and
411
, the request registers
403
and
413
, the relay registers
425
and
435
, the selection registers
423
and
433
, and the crossbar output data registers
450
and
451
retain an input data piece in response to a rise of a clock signal, and outputs a retained data piece in response to a fall of a clock signal.
Next, an operation of this system will be explained with reference to timing charts shown in
FIG. 10A
to
FIG. 10F
, by employing a case where the requester
400
outputs data pieces D
1
, D
2
, D
3
, . . . successively to the crossbar output port OP
0
, as an example. Note that it is assumed as a premise that an operation clock shown in
FIG. 10F
is supplied to each component.
First, the output data register
401
of the requester
400
outputs a data piece D
1
to the relay register
425
at the timing T
1
in accordance with the operation clock, as shown in FIG.
10
B. The relay register
425
outputs the data piece D
1
at the timing T
2
in accordance with the next operation clock, as shown in FIG.
10
D.
In the meantime, the request register
403
outputs request information corresponding to the data piece D
1
at the timing T
1
. The arbiter
422
arbitrates the output request, and sends a selection signal representing an arbitration result to the selection register
423
.
The selection register
423
outputs the selection signal for causing the data piece D
1
to be output, at the timing T
2
in response to the next operation clock, as shown in FIG.
10
D. The selector
424
selects and outputs a data piece supplied from either one of the relay registers
425
and
435
in accordance with the selection signal (in this example, the selector
424
selects the data piece D
1
from the relay register
425
).
The relay register
425
outputs the data piece D
1
at the timing T
2
in accordance with the next operation clock, as shown in FIG.
10
D. At the same timing, the selection register
423
outputs the selection signal (grant signal) to the selector
424
and to the output control circuit
402
, as shown in FIG.
10
A. The selector
424
transfers the data piece output from the relay register
425
to the crossbar output data register
450
.
The selection signal is also supplied to the output control circuit
402
. Thereby, the output control circuit
402
sets a data piece D
2
in the output data register
401
and sets request information corresponding to the data piece D
2
in the request register
403
at the timing T
2
. The data piece D
2
and the corresponding request information will be output at the timing T
3
.
The same operation will be repeated for the following data pieces. As described, according to this system, even though the data pieces can be successively output from the crossbar
440
without being stopped at the requester
400
due to an arbitration result, a dead cycle amounting to 1T (=1 clock cycle) is produced between the timing at which the requester
400
or
410
outputs a preceding data piece and the timing at which the requester
400
or
410
outputs the next data piece.
Suppose that a following data piece is to be set in the output data register
401
at the same timing at which a preceding data piece is output to the relay register
425
, in order to prevent the dead cycle from being produced. In this case, if the data pieces should be output successively and if the preceding data piece is stopped for a while from being output due to an arbitration result, the request information corresponding to the preceding data piece can not be saved from disappearing since the request information corresponding to the following data piece will be written upon the request information corresponding to the preceding data piece.
The crossbar having the structure described so far, needs to receive input of a next data piece and a request corresponding to the next data piece at a timing at which a preceding data piece is output therefrom or at a timing thereafter, in order to prevent disappearance of the request information of the data piece. As a result, the latency is long and the t
Knoll Clifford
NEC Corporation
Rinehart Mark H.
Young & Thompson
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