Crossbar switch architecture for multi-processor SoC platform

Details Crossbar switch architecture for multi-processor SoC platform Crossbar switch architecture for multi-processor SoC platform

2006-12-01

2009-06-30

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C370S375000, C327S403000, C327S407000, C327S415000

Reexamination Certificate

active

07554355

ABSTRACT:
Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

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