Cross point memory array using multiple modes of operation

Details Cross point memory array using multiple modes of operation Cross point memory array using multiple modes of operation

2002-12-26

2004-12-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000, C365S184000

Reexamination Certificate

active

06834008

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory, and more specifically to memory employing a cross point array.
2. Description of the Related Art
Conventional nonvolatile memory requires three terminal MOSFET-based devices. The layout of such devices are not ideal, usually requiring feature sizes of
8
B for each memory cell, where f is the minimum feature size.
However, not all memory elements require three terminals. Certain complex metal oxides (CMOs), for example, can retain a resistive state after being exposed to an electronic pulse, which can be generated from two terminals. U.S. Pat. No. 6,204,139, issued Mar. 20, 2001 to Liu et al.,.incorporated herein by reference for all purposes, describes some perovskite materials that exhibit such characteristics. The perovskite materials are also described by the same researchers in “Electric-pulse-induced reversible resistance change effect in magnetoresistive films,” Applied Physics Letters, Vol. 76, No. 19, 8 May 2000, and “A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films,” in materials for the 2001 Non-Volatile Memory Technology Symposium, all of which are hereby incorporated by reference for all purposes.
Similarly, the IBM Zurich Research Center has also published three technical papers that also discuss the use of metal oxide material for memory applications: “reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters, Vol. 77, No. 1, 3 Jul. 2000, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO
3
single crystals,” Applied Physics Letters, Vol. 78, No. 23, 4 Jun. 2001, and “Electric current distribution across a metal-insulator-metal structure during bistable switching,” Journal of Applied Physics, Vol. 90, No. 6, 15 Sep. 2001, all of which are hereby incorporated by reference for all purposes.
Similarly, magnetic RAM (MRAM) requires only two terminals to deliver a magnetic field to the memory element. Other two terminal devices include Ovonic Unified Memory (OUM), which uses chalcogenic layers of material, and various types of ferroelectric memory. With only two terminals, it has been theorized that memory can be arranged in a cross point architecture.
However, mere recognition that a two terminal memory element is theoretically capable of being placed in a cross point array does not solve many of the non-trivial problems associated with actually creating such a device.
SUMMARY OF THE INVENTION
The present invention provides a cross point memory array. In one embodiment, the memory array includes a first layer of conductive array lines, a second layer of conductive array lines and a plurality of memory plugs.
The first layer of conductive array lines are arranged so that they do not come into direct contact with each other. Similarly the second layer of conductive array lines are arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer. Each memory plug in the plurality of memory plugs are in electrical contact with one conductive array line from the first layer and one conductive array line from the second layer, the conductive array lines forming a unique pair for each memory plug.
Each memory plug has a memory element that, in a first write mode, switches from a first resistance state to a second resistance state upon application of a first write voltage pulse. In a second write mode the memory element reversibly switches from the second resistance state back to the first resistance state upon application of a second write voltage pulse to the memory element in a second write mode. In a read mode the memory element does not experience any significant resistive changes upon application of a read voltage. Both the first write mode and the second write mode is typically preceded by a read mode to determine the resistive state of the memory element.


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